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Searched refs:lane_mask (Results 1 - 12 of 12) sorted by relevance

/third_party/astc-encoder/Source/
H A Dastcenc_averages_and_directions.cpp71 vmask lane_mask = lane_id < vint(texel_count); in compute_partition_averages_rgb() local
74 vmask p0_mask = lane_mask & (texel_partition == vint(0)); in compute_partition_averages_rgb()
107 vmask lane_mask = lane_id < vint(texel_count); in compute_partition_averages_rgb()
110 vmask p0_mask = lane_mask & (texel_partition == vint(0)); in compute_partition_averages_rgb()
111 vmask p1_mask = lane_mask & (texel_partition == vint(1)); in compute_partition_averages_rgb()
152 vmask lane_mask = lane_id < vint(texel_count); in compute_partition_averages_rgb()
155 vmask p0_mask = lane_mask & (texel_partition == vint(0)); in compute_partition_averages_rgb()
156 vmask p1_mask = lane_mask & (texel_partition == vint(1)); in compute_partition_averages_rgb()
157 vmask p2_mask = lane_mask & (texel_partition == vint(2)); in compute_partition_averages_rgb()
242 vmask lane_mask
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H A Dastcenc_internal.h859 vmask4 lane_mask = vint4::lane_id() == vint4(channel); in is_constant_channel() local
861 return any(lane_mask & color_mask); in is_constant_channel()
/third_party/mesa3d/src/amd/compiler/
H A Daco_lower_phis.cpp69 return Operand(program->lane_mask); in get_ssa()
76 op = Operand::zero(program->lane_mask.bytes()); in get_ssa()
88 state->outputs[block_idx] = Operand(Temp(program->allocateTmp(program->lane_mask))); in get_ssa()
107 op = Operand(Temp(program->allocateTmp(program->lane_mask))); in get_ssa()
118 assert(op.size() == program->lane_mask.size()); in get_ssa()
144 cur = Operand::zero(program->lane_mask.bytes()); in build_merge_code()
349 if (phi->definitions[0].regClass() == program->lane_mask) in lower_phis()
H A Daco_optimizer_postRA.cpp228 Idx last_vcc_wr_idx = last_writer_idx(ctx, vcc, ctx.program->lane_mask); in try_apply_branch_vcc()
240 is_clobbered_since(ctx, exec, ctx.program->lane_mask, last_vcc_wr_idx) || in try_apply_branch_vcc()
241 is_clobbered_since(ctx, vcc, ctx.program->lane_mask, op0_instr_idx)) in try_apply_branch_vcc()
H A Daco_instruction_selection_setup.cpp244 return RegClass(RegType::sgpr, ctx->program->lane_mask.size() * components); in get_reg_class()
H A Daco_ir.cpp89 program->lane_mask = program->wave_size == 32 ? s1 : s2; in init_program()
H A Daco_optimizer.cpp2100 if (instr->definitions[0].regClass() != ctx.program->lane_mask) in combine_ordering_test()
2197 if (instr->definitions[0].regClass() != ctx.program->lane_mask) in combine_comparison_ordering()
2298 if (instr->definitions[0].regClass() != ctx.program->lane_mask) in combine_constant_comparison_ordering()
2838 Definition(ctx.program->allocateTmp(ctx.program->lane_mask)); in combine_add_sub_b2i()
H A Daco_ir.h2094 RegClass lane_mask;
H A Daco_spill.cpp1033 phi->operands[i] = Operand(exec, ctx.program->lane_mask); in add_coupling_code()
H A Daco_instruction_selection.cpp1101 assert(dst.regClass() == ctx->program->lane_mask);
10092 assert(instr->dest.ssa.bit_size != 1 || dst.regClass() == ctx->program->lane_mask);
10551 assert(cond.regClass() == ctx->program->lane_mask);
10819 assert(cond.regClass() == ctx->program->lane_mask);
/third_party/vixl/src/aarch64/
H A Dsimulator-aarch64.cc1352 uint16_t lane_mask, in Simulator()
1360 bool access = (lane_mask & (1 << (i * lane_size))) != 0; in Simulator()
1864 uint16_t lane_mask = GetPrintRegLaneMask(format); in Simulator() local
1865 PrintVRegistersForStructuredAccess(rt_code, reg_count, lane_mask, format); in Simulator()
1871 VIXL_ASSERT((lane_mask & access_mask) != 0); in Simulator()
1872 lane_mask = PrintPartialAccess(access_mask, in Simulator()
1873 lane_mask, in Simulator()
1895 uint16_t lane_mask = 1 << (lane * lane_size_in_bytes); in Simulator() local
1896 PrintVRegistersForStructuredAccess(rt_code, reg_count, lane_mask, format); in Simulator()
1897 PrintPartialAccess(lane_mask, in Simulator()
1351 PrintRegisterValueFPAnnotations(const uint8_t* value, uint16_t lane_mask, PrintRegisterFormat format) Simulator() argument
1913 uint16_t lane_mask = GetPrintRegLaneMask(format); Simulator() local
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H A Dsimulator-aarch64.h2641 // lane size is not respected when interpreting lane_mask: unaligned bits
2706 uint16_t lane_mask,
2710 uint16_t lane_mask,
2712 PrintRegisterValueFPAnnotations(sim_register.GetBytes(), lane_mask, format);

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