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Searched refs:kWRegSize (Results 1 - 25 of 25) sorted by relevance

/third_party/vixl/benchmarks/aarch64/
H A Dbench-utils.cc86 return PickBool() ? kWRegSize : kXRegSize; in PickRSize()
266 __ Pop(Register(static_cast<int>(GetRandomBits(2)) + 0, kWRegSize), in GenerateMemOperandSequence()
267 Register(static_cast<int>(GetRandomBits(2)) + 4, kWRegSize), in GenerateMemOperandSequence()
268 Register(static_cast<int>(GetRandomBits(2)) + 8, kWRegSize), in GenerateMemOperandSequence()
269 Register(static_cast<int>(GetRandomBits(2)) + 12, kWRegSize)); in GenerateMemOperandSequence()
H A Dbench-utils.h237 vixl::aarch64::Register PickW() { return PickR(vixl::aarch64::kWRegSize); } in PickW()
/third_party/node/deps/v8/src/regexp/arm64/
H A Dregexp-macro-assembler-arm64.cc832 const int align_mask = (alignment / kWRegSize) - 1; in GetCode()
835 static constexpr int kWRegPerXReg = kXRegSize / kWRegSize; in GetCode()
871 __ Cmp(x10, num_wreg_to_allocate * kWRegSize); in GetCode()
888 __ Claim(num_wreg_to_allocate, kWRegSize); in GetCode()
1395 kWRegSize - (kWRegSize * reg_from); in ClearRegisters()
1411 base_offset -= kWRegSize * 2; in ClearRegisters()
1567 -static_cast<int>(kWRegSize), in Push()
1576 MemOperand(backtrack_stackpointer(), kWRegSize, PostIndex)); in Pop()
1676 int offset = kFirstRegisterOnStack - register_index * kWRegSize; in register_location()
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H A Dregexp-macro-assembler-arm64.h130 static const int kFirstRegisterOnStack = kStackLocalPadding - kWRegSize;
/third_party/vixl/src/aarch64/
H A Dinstructions-aarch64.h59 const unsigned kWRegSize = 32; member
61 const unsigned kWRegSizeInBytes = kWRegSize / 8;
H A Dregisters-aarch64.h449 VIXL_STATIC_ASSERT(kSRegSize == kWRegSize);
807 V(WRegister, kWRegSize, Register) \
H A Dsimulator-aarch64.cc934 VIXL_ASSERT((reg_size == kXRegSize) || (reg_size == kWRegSize)); in Simulator()
936 uint64_t max_uint = (reg_size == kWRegSize) ? kWMaxUInt : kXMaxUInt; in Simulator()
937 uint64_t reg_mask = (reg_size == kWRegSize) ? kWRegMask : kXRegMask; in Simulator()
938 uint64_t sign_mask = (reg_size == kWRegSize) ? kWSignMask : kXSignMask; in Simulator()
1450 case kWRegSize: in Simulator()
3891 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; in Simulator()
3934 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; in Simulator()
3951 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; in Simulator()
3961 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; in Simulator()
4008 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; in Simulator()
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H A Doperands-aarch64.cc159 VIXL_ASSERT(reg.Is64Bits() || (shift_amount < kWRegSize)); in Operand()
H A Dinstructions-aarch64.cc610 unsigned reg_size = GetSixtyFourBits() ? kXRegSize : kWRegSize; in GetImmLogical()
H A Dassembler-aarch64.h7339 ((reg_size == kWRegSize) && IsUint5(imms)));
7346 ((reg_size == kWRegSize) && IsUint5(immr)));
7353 VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
7361 VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
7363 ((reg_size == kWRegSize) && IsUint5(immr)));
7374 VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
H A Ddisasm-aarch64.cc982 (instr->GetSixtyFourBits() == 1) ? kXRegSize : kWRegSize; in Disassembler()
1011 ((reg_size == kWRegSize) && (value <= 0xffffffff))); in Disassembler()
1029 if ((reg_size == kWRegSize) && (((value & 0xffff0000) == 0xffff0000) || in Disassembler()
1142 ((instr->GetSixtyFourBits() == 1) ? kXRegSize : kWRegSize) - 1; in Disassembler()
6476 reg_size = kWRegSize; in Disassembler()
7006 (instr->GetSixtyFourBits() == 1) ? kXRegSize : kWRegSize; in Disassembler()
H A Dassembler-aarch64.cc422 VIXL_ASSERT(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSize))); in tbz()
435 VIXL_ASSERT(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSize))); in tbnz()
5935 VIXL_ASSERT(((imm >> kWRegSize) == 0) ||
5936 ((imm >> (kWRegSize - 1)) == 0x1ffffffff));
6503 VIXL_ASSERT((reg_size == kXRegSize) || (reg_size == kWRegSize));
6562 if (width <= kWRegSize) {
6569 for (unsigned bits = width; bits <= kWRegSize; bits *= 2) {
H A Dmacro-assembler-aarch64.cc900 VIXL_ASSERT(((immediate >> kWRegSize) == 0) || in Emit()
901 ((immediate >> kWRegSize) == 0xffffffff)); in Emit()
H A Dmacro-assembler-aarch64.h975 // parameter. Only kXRegSize, kWRegSize, kDRegSize and kSRegSize are
995 void PushWRegList(RegList regs) { PushSizeRegList(regs, kWRegSize); } in PushWRegList()
996 void PopWRegList(RegList regs) { PopSizeRegList(regs, kWRegSize); } in PopWRegList()
1030 // parameter. Only kXRegSize, kWRegSize, kDRegSize and kSRegSize are
1062 PeekSizeRegList(regs, offset, kWRegSize); in PeekWRegList()
1065 PokeSizeRegList(regs, offset, kWRegSize); in PokeWRegList()
8747 return (vector.GetLaneSizeInBits() > kWRegSize) ? AcquireX() : AcquireW(); in AcquireRegisterToHoldLane()
H A Dsimulator-aarch64.h1564 case kWRegSize:
1702 case kWRegSize:
H A Dlogic-aarch64.cc7689 offset = ExtractUnsignedBitfield64(kWRegSize - 1, 0, offset);
7692 offset = ExtractSignedBitfield64(kWRegSize - 1, 0, offset);
/third_party/node/deps/v8/src/codegen/arm64/
H A Dinstructions-arm64.cc172 static_assert(kWRegSize == kSRegSize, "W and S registers must be same size."); in CalcLSPairDataSize()
H A Dconstants-arm64.h47 const int kWRegSize = kWRegSizeInBits >> 3; member
/third_party/vixl/test/aarch64/
H A Dtest-assembler-sve-aarch64.cc3828 CntHelper(config, &MacroAssembler::Cntw, 1, kWRegSize); in TEST_SVE()
3829 CntHelper(config, &MacroAssembler::Cntw, 2, kWRegSize); in TEST_SVE()
3830 CntHelper(config, &MacroAssembler::Cntw, 15, kWRegSize); in TEST_SVE()
3831 CntHelper(config, &MacroAssembler::Cntw, 16, kWRegSize); in TEST_SVE()
3856 DecHelper(config, &MacroAssembler::Decw, 1, kWRegSize, 42); in TEST_SVE()
3857 DecHelper(config, &MacroAssembler::Decw, 2, kWRegSize, -1); in TEST_SVE()
3858 DecHelper(config, &MacroAssembler::Decw, 15, kWRegSize, INT64_MIN); in TEST_SVE()
3859 DecHelper(config, &MacroAssembler::Decw, 16, kWRegSize, -42); in TEST_SVE()
3884 IncHelper(config, &MacroAssembler::Incw, 1, kWRegSize, 42); in TEST_SVE()
3885 IncHelper(config, &MacroAssembler::Incw, 2, kWRegSize, in TEST_SVE()
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H A Dtest-api-aarch64.cc232 VIXL_CHECK(Register(0, kWRegSize).Is(w0)); in TEST()
323 VIXL_CHECK(CPURegister(0, kWRegSize, CPURegister::kRegister).Is(w0)); in TEST()
962 Register r_w1(1, kWRegSize); in TEST()
1138 Register temp2 = temps.AcquireRegisterOfSize(kWRegSize); in TEST()
H A Dtest-assembler-aarch64.cc152 VIXL_ASSERT(!Assembler::IsImmLogical(0x1234, kWRegSize)); in TEST()
8227 ASSERT_EQUAL_64(((1 * base) >> kWRegSize) | ((2 * base) << kWRegSize), x15);
8230 ASSERT_EQUAL_32((4 * base) >> kWRegSize, w17);
8324 VIXL_CHECK(array[0] == (1 * low_base) + (2 * low_base << kWRegSize));
8325 VIXL_CHECK(array[1] == (3 * low_base) + (4 * low_base << kWRegSize));
8326 VIXL_CHECK(array[2] == (1 * low_base) + (2 * low_base << kWRegSize));
8327 VIXL_CHECK(array[3] == (3 * low_base) + (4 * low_base << kWRegSize));
8524 kWRegSize,
8529 kWRegSize,
[all...]
H A Dtest-utils-aarch64.cc507 w[i] = Register(n, kWRegSize); in PopulateRegisterArray()
H A Dtest-simulator-aarch64.cc979 VIXL_ASSERT((d_size == kXRegSize) || (d_size == kWRegSize)); in TestFPToFixed_Helper()
1045 VIXL_ASSERT((d_size == kXRegSize) || (d_size == kWRegSize)); in TestFPToInt_Helper()
H A Dtest-assembler-fp-aarch64.cc4633 __ Bfi(x11, x10, 0, kWRegSize);
4788 __ Bfi(x11, x10, 0, kWRegSize);
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-arm64.cc1049 static_assert((sizeof(T) == kWRegSize) || (sizeof(T) == kXRegSize), in AddWithCarry()
1235 static_assert(kWRegSize == kSRegSize, "W and S registers must be same size.");
1522 case kWRegSize:
2199 DCHECK_EQ(access_size, static_cast<unsigned>(kWRegSize));
2229 DCHECK_EQ(access_size, static_cast<unsigned>(kWRegSize));
2235 DCHECK_EQ(access_size, static_cast<unsigned>(kWRegSize));
2676 if (sizeof(T) == kWRegSize) {

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