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Searched refs:imm8 (Results 1 - 25 of 48) sorted by relevance

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/third_party/node/deps/v8/src/codegen/x64/
H A Dassembler-x64.h696 void instruction##l(Register dst, Immediate imm8) { \
697 shift(dst, imm8, subcode, kInt32Size); \
700 void instruction##q(Register dst, Immediate imm8) { \
701 shift(dst, imm8, subcode, kInt64Size); \
704 void instruction##l(Operand dst, Immediate imm8) { \
705 shift(dst, imm8, subcode, kInt32Size); \
708 void instruction##q(Operand dst, Immediate imm8) { \
709 shift(dst, imm8, subcode, kInt64Size); \
752 void btsq(Register dst, Immediate imm8);
753 void btrq(Register dst, Immediate imm8);
978 sse2_instr(XMMRegister reg, byte imm8, byte prefix, byte escape, byte opcode, int extension) sse2_instr() argument
1610 vshufps(XMMRegister dst, XMMRegister src1, XMMRegister src2, byte imm8) vshufps() argument
1613 vshufps(YMMRegister dst, YMMRegister src1, YMMRegister src2, byte imm8) vshufps() argument
1718 vinsertps(XMMRegister dst, XMMRegister src1, XMMRegister src2, byte imm8) vinsertps() argument
1723 vinsertps(XMMRegister dst, XMMRegister src1, Operand src2, byte imm8) vinsertps() argument
1727 vpextrq(Register dst, XMMRegister src, int8_t imm8) vpextrq() argument
1732 vpinsrb(XMMRegister dst, XMMRegister src1, Register src2, uint8_t imm8) vpinsrb() argument
1737 vpinsrb(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8) vpinsrb() argument
1741 vpinsrw(XMMRegister dst, XMMRegister src1, Register src2, uint8_t imm8) vpinsrw() argument
1746 vpinsrw(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8) vpinsrw() argument
1750 vpinsrd(XMMRegister dst, XMMRegister src1, Register src2, uint8_t imm8) vpinsrd() argument
1755 vpinsrd(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8) vpinsrd() argument
1759 vpinsrq(XMMRegister dst, XMMRegister src1, Register src2, uint8_t imm8) vpinsrq() argument
1764 vpinsrq(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8) vpinsrq() argument
1769 vpshufd(XMMRegister dst, XMMRegister src, uint8_t imm8) vpshufd() argument
1773 vpshufd(YMMRegister dst, YMMRegister src, uint8_t imm8) vpshufd() argument
1777 vpshufd(XMMRegister dst, Operand src, uint8_t imm8) vpshufd() argument
1781 vpshufd(YMMRegister dst, Operand src, uint8_t imm8) vpshufd() argument
1785 vpshuflw(XMMRegister dst, XMMRegister src, uint8_t imm8) vpshuflw() argument
1789 vpshuflw(YMMRegister dst, YMMRegister src, uint8_t imm8) vpshuflw() argument
1793 vpshuflw(XMMRegister dst, Operand src, uint8_t imm8) vpshuflw() argument
1797 vpshuflw(YMMRegister dst, Operand src, uint8_t imm8) vpshuflw() argument
1801 vpshufhw(XMMRegister dst, XMMRegister src, uint8_t imm8) vpshufhw() argument
1805 vpshufhw(YMMRegister dst, YMMRegister src, uint8_t imm8) vpshufhw() argument
1809 vpshufhw(XMMRegister dst, Operand src, uint8_t imm8) vpshufhw() argument
1813 vpshufhw(YMMRegister dst, Operand src, uint8_t imm8) vpshufhw() argument
1837 vpalignr(XMMRegister dst, XMMRegister src1, XMMRegister src2, uint8_t imm8) vpalignr() argument
1842 vpalignr(YMMRegister dst, YMMRegister src1, YMMRegister src2, uint8_t imm8) vpalignr() argument
1847 vpalignr(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8) vpalignr() argument
1851 vpalignr(YMMRegister dst, YMMRegister src1, Operand src2, uint8_t imm8) vpalignr() argument
[all...]
H A Dassembler-x64.cc883 void Assembler::btsq(Register dst, Immediate imm8) { in btsq() argument
889 emit(imm8.value_); in btsq()
892 void Assembler::btrq(Register dst, Immediate imm8) { in btrq() argument
898 emit(imm8.value_); in btrq()
1132 void Assembler::cmpb_al(Immediate imm8) { in cmpb_al() argument
1133 DCHECK(is_int8(imm8.value_) || is_uint8(imm8.value_)); in cmpb_al()
1136 emit(imm8.value_); in cmpb_al()
2843 void Assembler::pinsrw(XMMRegister dst, Register src, uint8_t imm8) { in pinsrw() argument
2850 emit(imm8); in pinsrw()
2853 pinsrw(XMMRegister dst, Operand src, uint8_t imm8) pinsrw() argument
2863 pextrq(Register dst, XMMRegister src, int8_t imm8) pextrq() argument
2875 pinsrq(XMMRegister dst, Register src, uint8_t imm8) pinsrq() argument
2887 pinsrq(XMMRegister dst, Operand src, uint8_t imm8) pinsrq() argument
2899 pinsrd(XMMRegister dst, Register src, uint8_t imm8) pinsrd() argument
2903 pinsrd(XMMRegister dst, Operand src, uint8_t imm8) pinsrd() argument
2908 pinsrb(XMMRegister dst, Register src, uint8_t imm8) pinsrb() argument
2912 pinsrb(XMMRegister dst, Operand src, uint8_t imm8) pinsrb() argument
2917 insertps(XMMRegister dst, XMMRegister src, byte imm8) insertps() argument
2923 insertps(XMMRegister dst, Operand src, byte imm8) insertps() argument
2985 shufps(XMMRegister dst, XMMRegister src, byte imm8) shufps() argument
3790 vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2, byte imm8) vps() argument
3800 vps(byte op, YMMRegister dst, YMMRegister src1, YMMRegister src2, byte imm8) vps() argument
4062 rorxq(Register dst, Register src, byte imm8) rorxq() argument
4073 rorxq(Register dst, Operand src, byte imm8) rorxq() argument
4084 rorxl(Register dst, Register src, byte imm8) rorxl() argument
4095 rorxl(Register dst, Operand src, byte imm8) rorxl() argument
4205 sse4_instr(XMMRegister dst, Register src, byte prefix, byte escape1, byte escape2, byte opcode, int8_t imm8) sse4_instr() argument
4244 sse4_instr(Register dst, XMMRegister src, byte prefix, byte escape1, byte escape2, byte opcode, int8_t imm8) sse4_instr() argument
4259 sse4_instr(Operand dst, XMMRegister src, byte prefix, byte escape1, byte escape2, byte opcode, int8_t imm8) sse4_instr() argument
[all...]
H A Dmacro-assembler-x64.cc892 void TurboAssembler::Pextrq(Register dst, XMMRegister src, int8_t imm8) { in CallRecordWriteStub() argument
895 vpextrq(dst, src, imm8); in CallRecordWriteStub()
898 pextrq(dst, src, imm8); in CallRecordWriteStub()
2069 uint8_t imm8) { in CallRecordWriteStub()
2070 if (imm8 == 0) { in CallRecordWriteStub()
2074 DCHECK_EQ(1, imm8); in CallRecordWriteStub()
2082 uint8_t imm8, uint32_t* load_pc_offset) { in CallRecordWriteStub()
2085 if (imm8 == 1) { in CallRecordWriteStub()
2088 DCHECK_EQ(0, imm8); in CallRecordWriteStub()
2094 void TurboAssembler::PinsrdPreSse41(XMMRegister dst, Register src, uint8_t imm8, in CallRecordWriteStub() argument
2068 PextrdPreSse41(Register dst, XMMRegister src, uint8_t imm8) CallRecordWriteStub() argument
2081 PinsrdPreSse41Helper(TurboAssembler* tasm, XMMRegister dst, Op src, uint8_t imm8, uint32_t* load_pc_offset) CallRecordWriteStub() argument
2099 PinsrdPreSse41(XMMRegister dst, Operand src, uint8_t imm8, uint32_t* load_pc_offset) CallRecordWriteStub() argument
2104 Pinsrq(XMMRegister dst, XMMRegister src1, Register src2, uint8_t imm8, uint32_t* load_pc_offset) CallRecordWriteStub() argument
2110 Pinsrq(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8, uint32_t* load_pc_offset) CallRecordWriteStub() argument
[all...]
H A Dmacro-assembler-x64.h175 void PextrdPreSse41(Register dst, XMMRegister src, uint8_t imm8);
176 void Pextrq(Register dst, XMMRegister src, int8_t imm8);
178 void PinsrdPreSse41(XMMRegister dst, Register src2, uint8_t imm8,
180 void PinsrdPreSse41(XMMRegister dst, Operand src2, uint8_t imm8,
183 void Pinsrq(XMMRegister dst, XMMRegister src1, Register src2, uint8_t imm8,
185 void Pinsrq(XMMRegister dst, XMMRegister src1, Operand src2, uint8_t imm8,
/third_party/node/deps/v8/src/codegen/ia32/
H A Dassembler-ia32.cc903 void Assembler::cmpb(Operand op, Immediate imm8) { in cmpb() argument
904 DCHECK(imm8.is_int8() || imm8.is_uint8()); in cmpb()
912 emit_b(imm8); in cmpb()
1137 void Assembler::rcl(Register dst, uint8_t imm8) { in rcl() argument
1139 DCHECK(is_uint5(imm8)); // illegal shift count in rcl()
1140 if (imm8 == 1) { in rcl()
1146 EMIT(imm8); in rcl()
1150 void Assembler::rcr(Register dst, uint8_t imm8) { in rcr() argument
1152 DCHECK(is_uint5(imm8)); // illega in rcr()
1163 rol(Operand dst, uint8_t imm8) rol() argument
1182 ror(Operand dst, uint8_t imm8) ror() argument
1201 sar(Operand dst, uint8_t imm8) sar() argument
1242 shl(Operand dst, uint8_t imm8) shl() argument
1261 shr(Operand dst, uint8_t imm8) shr() argument
1366 test_b(Register reg, Immediate imm8) test_b() argument
1384 test_b(Operand op, Immediate imm8) test_b() argument
2385 shufps(XMMRegister dst, XMMRegister src, byte imm8) shufps() argument
2394 shufpd(XMMRegister dst, XMMRegister src, byte imm8) shufpd() argument
2552 extractps(Operand dst, XMMRegister src, byte imm8) extractps() argument
2564 extractps(Register dst, XMMRegister src, byte imm8) extractps() argument
2877 vshufpd(XMMRegister dst, XMMRegister src1, Operand src2, byte imm8) vshufpd() argument
2920 vshufps(XMMRegister dst, XMMRegister src1, Operand src2, byte imm8) vshufps() argument
2927 vpsllw(XMMRegister dst, XMMRegister src, uint8_t imm8) vpsllw() argument
2933 vpslld(XMMRegister dst, XMMRegister src, uint8_t imm8) vpslld() argument
2939 vpsllq(XMMRegister dst, XMMRegister src, uint8_t imm8) vpsllq() argument
2945 vpsrlw(XMMRegister dst, XMMRegister src, uint8_t imm8) vpsrlw() argument
2951 vpsrld(XMMRegister dst, XMMRegister src, uint8_t imm8) vpsrld() argument
2957 vpsrlq(XMMRegister dst, XMMRegister src, uint8_t imm8) vpsrlq() argument
2963 vpsraw(XMMRegister dst, XMMRegister src, uint8_t imm8) vpsraw() argument
2969 vpsrad(XMMRegister dst, XMMRegister src, uint8_t imm8) vpsrad() argument
3102 vextractps(Operand dst, XMMRegister src, byte imm8) vextractps() argument
3155 rorx(Register dst, Operand src, byte imm8) rorx() argument
3327 emit_arith_b(int op1, int op2, Register dst, int imm8) emit_arith_b() argument
[all...]
H A Dassembler-ia32.h494 void mov_b(Register dst, int8_t imm8) { mov_b(Operand(dst), imm8); } in mov_b() local
586 void cmpb(Register reg, Immediate imm8) { in cmpb() argument
588 cmpb(Operand(reg), imm8); in cmpb() local
590 void cmpb(Operand op, Immediate imm8);
651 void rcl(Register dst, uint8_t imm8);
652 void rcr(Register dst, uint8_t imm8);
654 void rol(Register dst, uint8_t imm8) { rol(Operand(dst), imm8); } in rol() local
655 void rol(Operand dst, uint8_t imm8);
659 void ror(Register dst, uint8_t imm8) { ror(Operand(dst), imm8); } ror() local
664 void sar(Register dst, uint8_t imm8) { sar(Operand(dst), imm8); } sar() local
672 void shl(Register dst, uint8_t imm8) { shl(Operand(dst), imm8); } shl() local
679 void shr(Register dst, uint8_t imm8) { shr(Operand(dst), imm8); } shr() local
1162 vshufps(XMMRegister dst, XMMRegister src1, XMMRegister src2, byte imm8) vshufps() argument
1166 vshufpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, byte imm8) vshufpd() argument
1423 rorx(Register dst, Register src, byte imm8) rorx() argument
[all...]
H A Dmacro-assembler-ia32.h221 void ShlPair(Register high, Register low, uint8_t imm8);
223 void ShrPair(Register high, Register low, uint8_t imm8);
225 void SarPair(Register high, Register low, uint8_t imm8);
307 void PextrdPreSse41(Register dst, XMMRegister src, uint8_t imm8);
308 void PinsrdPreSse41(XMMRegister dst, Register src, uint8_t imm8, in PinsrdPreSse41() argument
310 PinsrdPreSse41(dst, Operand(src), imm8, load_pc_offset); in PinsrdPreSse41()
312 void PinsrdPreSse41(XMMRegister dst, Operand src, uint8_t imm8,
H A Dmacro-assembler-ia32.cc1601 uint8_t imm8) { in CallRecordWriteStub()
1602 if (imm8 == 0) { in CallRecordWriteStub()
1609 DCHECK_LT(imm8, 2); in CallRecordWriteStub()
1612 mov(dst, Operand(esp, imm8 * kUInt32Size)); in CallRecordWriteStub()
1616 void TurboAssembler::PinsrdPreSse41(XMMRegister dst, Operand src, uint8_t imm8, in CallRecordWriteStub() argument
1621 DCHECK_LT(imm8, 2); in CallRecordWriteStub()
1625 // Overwrite the portion specified in {imm8}. in CallRecordWriteStub()
1627 mov(Operand(esp, imm8 * kUInt32Size), src.reg()); in CallRecordWriteStub()
1630 movss(Operand(esp, imm8 * kUInt32Size), dst); in CallRecordWriteStub()
1600 PextrdPreSse41(Register dst, XMMRegister src, uint8_t imm8) CallRecordWriteStub() argument
/third_party/node/deps/v8/src/codegen/shared-ia32-x64/
H A Dmacro-assembler-shared-ia32-x64.h57 void Pinsrb(XMMRegister dst, XMMRegister src1, Op src2, uint8_t imm8, in Pinsrb() argument
60 imm8, load_pc_offset, {SSE4_1}); in Pinsrb()
64 void Pinsrw(XMMRegister dst, XMMRegister src1, Op src2, uint8_t imm8, in Pinsrw() argument
67 imm8, load_pc_offset); in Pinsrw()
94 uint8_t imm8);
496 XMMRegister dst, XMMRegister src1, Op src2, uint8_t imm8, in PinsrHelper()
502 (assm->*avx)(dst, src1, src2, imm8); in PinsrHelper()
511 (assm->*noavx)(dst, src2, imm8); in PinsrHelper()
513 (assm->*noavx)(dst, src2, imm8); in PinsrHelper()
563 void Pextrd(Register dst, XMMRegister src, uint8_t imm8) { in Pextrd() argument
495 PinsrHelper(Assembler* assm, AvxFn<Op> avx, NoAvxFn<Op> noavx, XMMRegister dst, XMMRegister src1, Op src2, uint8_t imm8, uint32_t* load_pc_offset = nullptr, base::Optional<CpuFeature> feature = base::nullopt) PinsrHelper() argument
582 Pinsrd(XMMRegister dst, XMMRegister src1, Op src2, uint8_t imm8, uint32_t* load_pc_offset = nullptr) Pinsrd() argument
597 Pinsrd(XMMRegister dst, Op src, uint8_t imm8, uint32_t* load_pc_offset = nullptr) Pinsrd() argument
[all...]
/third_party/node/deps/openssl/openssl/crypto/perlasm/
H A Dppc-xlate.pl367 my ($f, $vrt, $imm8) = @_;
368 $imm8 = oct($imm8) if ($imm8 =~ /^0/);
369 $imm8 &= 0xff;
370 " .long ".sprintf "0x%X",(60<<26)|($vrt<<21)|($imm8<<11)|(360<<1)|1;
/third_party/openssl/crypto/perlasm/
H A Dppc-xlate.pl367 my ($f, $vrt, $imm8) = @_;
368 $imm8 = oct($imm8) if ($imm8 =~ /^0/);
369 $imm8 &= 0xff;
370 " .long ".sprintf "0x%X",(60<<26)|($vrt<<21)|($imm8<<11)|(360<<1)|1;
/third_party/vixl/src/aarch32/
H A Dinstructions-aarch32.cc629 uint32_t imm8 = imm >> (24 - shift); in ImmediateT32() local
631 if ((imm8 <= 0xff) && ((imm8 & 0x80) != 0) && (overflow == 0)) { in ImmediateT32()
632 SetEncodingValue(((shift + 8) << 7) | (imm8 & 0x7F)); in ImmediateT32()
686 uint32_t imm8 = (imm << rot) | (imm >> (32 - rot)); in ImmediateA32() local
687 if (imm8 <= 0xff) { in ImmediateA32()
688 SetEncodingValue((rot << 7) | imm8); in ImmediateA32()
H A Doperands-aarch32.h540 static float Decode(uint32_t imm8, const FloatType<float>&) { in Decode() argument
541 return VFP::Imm8ToFP32(imm8); in Decode()
544 static double Decode(uint32_t imm8, const FloatType<double>&) { in Decode() argument
545 return VFP::Imm8ToFP64(imm8); in Decode()
613 // - an immediate constant, such as <imm8>, <imm12>
/third_party/node/deps/v8/src/diagnostics/ia32/
H A Ddisasm-ia32.cc589 int imm8 = -1; in D1D3C1Instruction() local
619 imm8 = 1; in D1D3C1Instruction()
621 imm8 = *(data + 1); in D1D3C1Instruction()
626 if (imm8 >= 0) { in D1D3C1Instruction()
627 AppendToBuffer(",%d", imm8); in D1D3C1Instruction()
1990 // shufps xmm, xmm/m128, imm8 in InstructionDecode()
1992 int8_t imm8 = static_cast<int8_t>(data[1]); in InstructionDecode() local
1994 NameOfXMMRegister(regop), static_cast<int>(imm8)); in InstructionDecode()
2015 int8_t imm8 = static_cast<int8_t>(data[1]); in InstructionDecode() local
2018 NameOfCPURegister(regop), static_cast<int>(imm8)); in InstructionDecode()
2275 int8_t imm8 = static_cast<int8_t>(data[1]); InstructionDecode() local
2324 int8_t imm8 = static_cast<int8_t>(data[1]); InstructionDecode() local
2427 int8_t imm8 = static_cast<int8_t>(data[1]); InstructionDecode() local
2435 int8_t imm8 = static_cast<int8_t>(data[1]); InstructionDecode() local
2443 int8_t imm8 = static_cast<int8_t>(data[1]); InstructionDecode() local
[all...]
/third_party/vixl/src/aarch64/
H A Dmacro-assembler-sve-aarch64.cc75 int imm8; in TrySingleAddSub() local
77 if (imm.TryEncodeAsShiftedUintNForLane<8, 0>(zd, &imm8, &shift) || in TrySingleAddSub()
78 imm.TryEncodeAsShiftedUintNForLane<8, 8>(zd, &imm8, &shift)) { in TrySingleAddSub()
82 add(zd, zd, imm8, shift); in TrySingleAddSub()
85 sub(zd, zd, imm8, shift); in TrySingleAddSub()
368 int imm8; in Cpy() local
370 if (imm.TryEncodeAsShiftedIntNForLane<8, 0>(zd, &imm8, &shift) || in Cpy()
371 imm.TryEncodeAsShiftedIntNForLane<8, 8>(zd, &imm8, &shift)) { in Cpy()
373 cpy(zd, pg, imm8, shift); in Cpy()
482 int imm8; in Dup() local
1095 int imm8; Sub() local
[all...]
H A Dinstructions-aarch64.cc772 Float16 Instruction::Imm8ToFloat16(uint32_t imm8) { in Imm8ToFloat16() argument
776 uint32_t bits = imm8; in Imm8ToFloat16()
785 float Instruction::Imm8ToFP32(uint32_t imm8) { in Imm8ToFP32() argument
789 uint32_t bits = imm8; in Imm8ToFP32()
805 double Instruction::Imm8ToFP64(uint32_t imm8) { in Imm8ToFP64() argument
810 uint32_t bits = imm8; in Imm8ToFP64()
H A Dassembler-sve-aarch64.cc32 void Assembler::ResolveSVEImm8Shift(int* imm8, int* shift) { in ResolveSVEImm8Shift() argument
36 if (IsInt8(*imm8)) { in ResolveSVEImm8Shift()
38 } else if ((*imm8 % 256) == 0) { in ResolveSVEImm8Shift()
39 *imm8 /= 256; in ResolveSVEImm8Shift()
44 VIXL_ASSERT(IsInt8(*imm8)); in ResolveSVEImm8Shift()
3560 int imm8, in cpy()
3564 // size<23:22> | Pg<19:16> | M<14> | sh<13> | imm8<12:5> | Zd<4:0> in cpy()
3569 ResolveSVEImm8Shift(&imm8, &shift); in cpy()
3574 ImmField<12, 5>(imm8)); in cpy()
3580 // size<23:22> | Pg<19:16> | imm8<1 in fcpy()
3558 cpy(const ZRegister& zd, const PRegister& pg, int imm8, int shift) cpy() argument
3591 SVEIntAddSubtractImmUnpredicatedHelper( SVEIntAddSubtractImm_UnpredicatedOp op, const ZRegister& zd, int imm8, int shift) SVEIntAddSubtractImmUnpredicatedHelper() argument
3614 add(const ZRegister& zd, const ZRegister& zn, int imm8, int shift) add() argument
3630 dup(const ZRegister& zd, int imm8, int shift) dup() argument
3656 mul(const ZRegister& zd, const ZRegister& zn, int imm8) mul() argument
3669 smax(const ZRegister& zd, const ZRegister& zn, int imm8) smax() argument
3682 smin(const ZRegister& zd, const ZRegister& zn, int imm8) smin() argument
3695 sqadd(const ZRegister& zd, const ZRegister& zn, int imm8, int shift) sqadd() argument
3711 sqsub(const ZRegister& zd, const ZRegister& zn, int imm8, int shift) sqsub() argument
3727 sub(const ZRegister& zd, const ZRegister& zn, int imm8, int shift) sub() argument
3743 subr(const ZRegister& zd, const ZRegister& zn, int imm8, int shift) subr() argument
3759 umax(const ZRegister& zd, const ZRegister& zn, int imm8) umax() argument
3772 umin(const ZRegister& zd, const ZRegister& zn, int imm8) umin() argument
3785 uqadd(const ZRegister& zd, const ZRegister& zn, int imm8, int shift) uqadd() argument
3801 uqsub(const ZRegister& zd, const ZRegister& zn, int imm8, int shift) uqsub() argument
6535 mov(const ZRegister& zd, const PRegister& pg, int imm8, int shift) mov() argument
6589 mov(const ZRegister& zd, int imm8, int shift) mov() argument
[all...]
H A Dassembler-aarch64.h2740 void orr(const VRegister& vd, const int imm8, const int left_shift = 0);
2752 void bic(const VRegister& vd, const int imm8, const int left_shift = 0);
2780 const int imm8,
3661 void add(const ZRegister& zd, const ZRegister& zn, int imm8, int shift = -1);
4004 void cpy(const ZRegister& zd, const PRegister& pg, int imm8, int shift = -1);
4057 void dup(const ZRegister& zd, int imm8, int shift = -1);
5072 void mov(const ZRegister& zd, const PRegister& pg, int imm8, int shift = -1);
5075 void mov(const ZRegister& zd, int imm8, int shift);
5108 void mul(const ZRegister& zd, const ZRegister& zn, int imm8);
5317 void smax(const ZRegister& zd, const ZRegister& zn, int imm8);
[all...]
/third_party/node/deps/v8/src/codegen/arm64/
H A Dinstructions-arm64.h180 static float Imm8ToFP32(uint32_t imm8) { in Imm8ToFP32() argument
184 uint32_t bits = imm8; in Imm8ToFP32()
193 static double Imm8ToFP64(uint32_t imm8) { in Imm8ToFP64() argument
198 uint32_t bits = imm8; in Imm8ToFP64()
H A Dassembler-arm64.h479 void bic(const VRegister& vd, const int imm8, const int left_shift = 0);
504 void mvni(const VRegister& vd, const int imm8, Shift shift = LSL,
568 void orr(const VRegister& vd, const int imm8, const int left_shift = 0);
2345 static Instr ImmNEONabcdefgh(int imm8) {
2346 DCHECK(is_uint8(imm8));
2348 instr = ((imm8 >> 5) & 7) << ImmNEONabc_offset;
2349 instr |= (imm8 & 0x1f) << ImmNEONdefgh_offset;
2552 void NEONModifiedImmShiftLsl(const VRegister& vd, const int imm8,
2555 void NEONModifiedImmShiftMsl(const VRegister& vd, const int imm8,
/third_party/ffmpeg/libavfilter/x86/
H A Dvf_gblur.asm247 %assign %%imm8 %1
250 vinserti64x4 m%1, m%2, ym%3, %%imm8
256 %assign %%imm8 %1
259 vextractf64x4 ym%1, m%1, %%imm8
260 vextractf64x4 ym%2, m%2, %%imm8
261 vinserti64x4 m%1, m%1, ym%2, %%imm8
/third_party/node/deps/v8/src/diagnostics/mips64/
H A Ddisasm-mips64.cc901 DCHECK(STRING_STARTS_WITH(format, "imm8")); in FormatOption()
2307 Format(instr, "andi.b 'wd, 'ws, 'imm8"); in DecodeTypeMsaI8()
2310 Format(instr, "ori.b 'wd, 'ws, 'imm8"); in DecodeTypeMsaI8()
2313 Format(instr, "nori.b 'wd, 'ws, 'imm8"); in DecodeTypeMsaI8()
2316 Format(instr, "xori.b 'wd, 'ws, 'imm8"); in DecodeTypeMsaI8()
2319 Format(instr, "bmnzi.b 'wd, 'ws, 'imm8"); in DecodeTypeMsaI8()
2322 Format(instr, "bmzi.b 'wd, 'ws, 'imm8"); in DecodeTypeMsaI8()
2325 Format(instr, "bseli.b 'wd, 'ws, 'imm8"); in DecodeTypeMsaI8()
2328 Format(instr, "shf.b 'wd, 'ws, 'imm8"); in DecodeTypeMsaI8()
2331 Format(instr, "shf.h 'wd, 'ws, 'imm8"); in DecodeTypeMsaI8()
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/third_party/node/deps/v8/src/diagnostics/mips/
H A Ddisasm-mips.cc860 DCHECK(STRING_STARTS_WITH(format, "imm8")); in FormatOption()
2020 Format(instr, "andi.b 'wd, 'ws, 'imm8"); in DecodeTypeMsaI8()
2023 Format(instr, "ori.b 'wd, 'ws, 'imm8"); in DecodeTypeMsaI8()
2026 Format(instr, "nori.b 'wd, 'ws, 'imm8"); in DecodeTypeMsaI8()
2029 Format(instr, "xori.b 'wd, 'ws, 'imm8"); in DecodeTypeMsaI8()
2032 Format(instr, "bmnzi.b 'wd, 'ws, 'imm8"); in DecodeTypeMsaI8()
2035 Format(instr, "bmzi.b 'wd, 'ws, 'imm8"); in DecodeTypeMsaI8()
2038 Format(instr, "bseli.b 'wd, 'ws, 'imm8"); in DecodeTypeMsaI8()
2041 Format(instr, "shf.b 'wd, 'ws, 'imm8"); in DecodeTypeMsaI8()
2044 Format(instr, "shf.h 'wd, 'ws, 'imm8"); in DecodeTypeMsaI8()
[all...]
/third_party/node/deps/v8/src/codegen/mips64/
H A Dassembler-mips64.h922 void andi_b(MSARegister wd, MSARegister ws, uint32_t imm8);
923 void ori_b(MSARegister wd, MSARegister ws, uint32_t imm8);
924 void nori_b(MSARegister wd, MSARegister ws, uint32_t imm8);
925 void xori_b(MSARegister wd, MSARegister ws, uint32_t imm8);
926 void bmnzi_b(MSARegister wd, MSARegister ws, uint32_t imm8);
927 void bmzi_b(MSARegister wd, MSARegister ws, uint32_t imm8);
928 void bseli_b(MSARegister wd, MSARegister ws, uint32_t imm8);
929 void shf_b(MSARegister wd, MSARegister ws, uint32_t imm8);
930 void shf_h(MSARegister wd, MSARegister ws, uint32_t imm8);
931 void shf_w(MSARegister wd, MSARegister ws, uint32_t imm8);
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/third_party/node/deps/v8/src/codegen/mips/
H A Dassembler-mips.h862 void andi_b(MSARegister wd, MSARegister ws, uint32_t imm8);
863 void ori_b(MSARegister wd, MSARegister ws, uint32_t imm8);
864 void nori_b(MSARegister wd, MSARegister ws, uint32_t imm8);
865 void xori_b(MSARegister wd, MSARegister ws, uint32_t imm8);
866 void bmnzi_b(MSARegister wd, MSARegister ws, uint32_t imm8);
867 void bmzi_b(MSARegister wd, MSARegister ws, uint32_t imm8);
868 void bseli_b(MSARegister wd, MSARegister ws, uint32_t imm8);
869 void shf_b(MSARegister wd, MSARegister ws, uint32_t imm8);
870 void shf_h(MSARegister wd, MSARegister ws, uint32_t imm8);
871 void shf_w(MSARegister wd, MSARegister ws, uint32_t imm8);
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