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Searched refs:gfx_level (Results 1 - 25 of 173) sorted by relevance

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/third_party/mesa3d/src/amd/common/
H A Dac_debug.c70 enum amd_gfx_level gfx_level; member
112 static const struct si_reg *find_register(enum amd_gfx_level gfx_level, unsigned offset) in find_register() argument
117 switch (gfx_level) { in find_register()
157 const char *ac_get_register_name(enum amd_gfx_level gfx_level, unsigned offset) in ac_get_register_name() argument
159 const struct si_reg *reg = find_register(gfx_level, offset); in ac_get_register_name()
164 void ac_dump_reg(FILE *file, enum amd_gfx_level gfx_level, unsigned offset, uint32_t value, in ac_dump_reg() argument
167 const struct si_reg *reg = find_register(gfx_level, offset); in ac_dump_reg()
255 ac_dump_reg(f, ib->gfx_level, reg + i * 4, ac_ib_get(ib), ~0); in ac_parse_set_reg_packet()
300 if (ib->gfx_level >= GFX11 && G_585_PWS_ENA(ib->ib[ib->cur_dw + 5])) { in ac_parse_packet3()
301 ac_dump_reg(f, ib->gfx_level, R_580_ACQUIRE_MEM_PWS_ in ac_parse_packet3()
611 ac_parse_ib_chunk(FILE *f, uint32_t *ib_ptr, int num_dw, const int *trace_ids, unsigned trace_id_count, enum amd_gfx_level gfx_level, ac_debug_addr_callback addr_callback, void *addr_callback_data) ac_parse_ib_chunk() argument
658 ac_parse_ib(FILE *f, uint32_t *ib, int num_dw, const int *trace_ids, unsigned trace_id_count, const char *name, enum amd_gfx_level gfx_level, ac_debug_addr_callback addr_callback, void *addr_callback_data) ac_parse_ib() argument
677 ac_vm_fault_occured(enum amd_gfx_level gfx_level, uint64_t *old_dmesg_timestamp, uint64_t *out_addr) ac_vm_fault_occured() argument
815 ac_get_wave_info(enum amd_gfx_level gfx_level, struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP]) ac_get_wave_info() argument
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H A Dac_gpu_info.c419 if (info->gfx_level < GFX9) in has_tmz_support()
850 info->gfx_level = GFX11; in ac_query_gpu_info()
852 info->gfx_level = GFX10_3; in ac_query_gpu_info()
854 info->gfx_level = GFX10; in ac_query_gpu_info()
856 info->gfx_level = GFX9; in ac_query_gpu_info()
858 info->gfx_level = GFX8; in ac_query_gpu_info()
860 info->gfx_level = GFX7; in ac_query_gpu_info()
862 info->gfx_level = GFX6; in ac_query_gpu_info()
870 info->gfx_level >= GFX10_3 && in ac_query_gpu_info()
897 info->has_l2_uncached = info->gfx_level > in ac_query_gpu_info()
1630 ac_get_gs_table_depth(enum amd_gfx_level gfx_level, enum radeon_family family) ac_get_gs_table_depth() argument
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H A Dac_shader_util.c92 uint32_t ac_vgt_gs_mode(unsigned gs_max_vert_out, enum amd_gfx_level gfx_level) in ac_vgt_gs_mode() argument
96 assert (gfx_level < GFX11); in ac_vgt_gs_mode()
110 S_028A40_ES_WRITE_OPTIMIZE(gfx_level <= GFX8) | S_028A40_GS_WRITE_OPTIMIZE(1) | in ac_vgt_gs_mode()
111 S_028A40_ONCHIP(gfx_level >= GFX9 ? 1 : 0); in ac_vgt_gs_mode()
116 unsigned ac_get_tbuffer_format(enum amd_gfx_level gfx_level, unsigned dfmt, unsigned nfmt) in ac_get_tbuffer_format() argument
123 if (gfx_level >= GFX11) { in ac_get_tbuffer_format()
318 } else if (gfx_level >= GFX10) { in ac_get_tbuffer_format()
424 enum ac_image_dim ac_get_sampler_dim(enum amd_gfx_level gfx_level, enum glsl_sampler_dim dim, in ac_get_sampler_dim() argument
429 if (gfx_level == GFX9) in ac_get_sampler_dim()
451 enum ac_image_dim ac_get_image_dim(enum amd_gfx_level gfx_level, enu argument
731 ac_compute_lshs_workgroup_size(enum amd_gfx_level gfx_level, gl_shader_stage stage, unsigned tess_num_patches, unsigned tess_patch_in_vtx, unsigned tess_patch_out_vtx) ac_compute_lshs_workgroup_size() argument
754 ac_compute_esgs_workgroup_size(enum amd_gfx_level gfx_level, unsigned wave_size, unsigned es_verts, unsigned gs_inst_prims) ac_compute_esgs_workgroup_size() argument
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H A Dac_surface_test_common.h38 info->gfx_level = GFX9; in init_vega10()
53 info->gfx_level = GFX9; in init_vega20()
69 info->gfx_level = GFX9; in init_raven()
84 info->gfx_level = GFX9; in init_raven2()
99 info->gfx_level = GFX10; in init_navi10()
113 info->gfx_level = GFX10; in init_navi14()
127 info->gfx_level = GFX10_3; in init_gfx103()
143 info->gfx_level = GFX11; in init_gfx11()
195 switch(info.gfx_level) { in get_radeon_info()
216 info.max_render_backends = info.gfx_level in get_radeon_info()
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H A Dac_debug.h59 const char *ac_get_register_name(enum amd_gfx_level gfx_level, unsigned offset);
60 void ac_dump_reg(FILE *file, enum amd_gfx_level gfx_level, unsigned offset, uint32_t value,
63 unsigned trace_id_count, enum amd_gfx_level gfx_level,
66 const char *name, enum amd_gfx_level gfx_level, ac_debug_addr_callback addr_callback,
69 bool ac_vm_fault_occured(enum amd_gfx_level gfx_level, uint64_t *old_dmesg_timestamp,
72 unsigned ac_get_wave_info(enum amd_gfx_level gfx_level,
H A Dac_nir_lower_esgs_io_to_mem.c45 enum amd_gfx_level gfx_level; member
166 if (st->gfx_level <= GFX8) { in lower_es_output_store()
193 if (st->gfx_level < GFX9) { in gs_get_vertex_offset()
198 assert(st->gfx_level == GFX9); in gs_get_vertex_offset()
258 nir_ssa_def *vertex_offset = st->gfx_level >= GFX9 in gs_per_vertex_input_offset()
262 unsigned base_stride = st->gfx_level >= GFX9 ? 1 : 64 /* Wave size on GFX6-8 */; in gs_per_vertex_input_offset()
277 if (st->gfx_level >= GFX9) in lower_gs_per_vertex_input_load()
296 enum amd_gfx_level gfx_level, in ac_nir_lower_es_outputs_to_mem()
300 .gfx_level = gfx_level, in ac_nir_lower_es_outputs_to_mem()
294 ac_nir_lower_es_outputs_to_mem(nir_shader *shader, ac_nir_map_io_driver_location map, enum amd_gfx_level gfx_level, unsigned esgs_itemsize) ac_nir_lower_es_outputs_to_mem() argument
312 ac_nir_lower_gs_inputs_to_mem(nir_shader *shader, ac_nir_map_io_driver_location map, enum amd_gfx_level gfx_level, bool triangle_strip_adjacency_fix) ac_nir_lower_gs_inputs_to_mem() argument
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H A Dac_shader_util.h98 uint32_t ac_vgt_gs_mode(unsigned gs_max_vert_out, enum amd_gfx_level gfx_level);
100 unsigned ac_get_tbuffer_format(enum amd_gfx_level gfx_level, unsigned dfmt, unsigned nfmt);
104 enum ac_image_dim ac_get_sampler_dim(enum amd_gfx_level gfx_level, enum glsl_sampler_dim dim,
107 enum ac_image_dim ac_get_image_dim(enum amd_gfx_level gfx_level, enum glsl_sampler_dim sdim,
123 unsigned ac_compute_lshs_workgroup_size(enum amd_gfx_level gfx_level, gl_shader_stage stage,
128 unsigned ac_compute_esgs_workgroup_size(enum amd_gfx_level gfx_level, unsigned wave_size,
H A Dac_surface.c125 bool ac_surface_supports_dcc_image_stores(enum amd_gfx_level gfx_level, in ac_surface_supports_dcc_image_stores() argument
129 if (gfx_level < GFX10) in ac_surface_supports_dcc_image_stores()
154 (gfx_level >= GFX10_3 && /* gfx10.3 */ in ac_surface_supports_dcc_image_stores()
202 if (info->gfx_level < GFX9) in ac_is_modifier_supported()
209 if (info->gfx_level < GFX9 && util_format_get_num_planes(format) > 1) in ac_is_modifier_supported()
213 switch(info->gfx_level) { in ac_is_modifier_supported()
267 switch (info->gfx_level) { in ac_get_supported_modifiers()
343 bool rbplus = info->gfx_level >= GFX10_3; in ac_get_supported_modifiers()
360 if (info->gfx_level >= GFX10_3) { in ac_get_supported_modifiers()
847 if (info->gfx_level > in gfx6_set_micro_tile_mode()
2965 ac_surface_get_plane_offset(enum amd_gfx_level gfx_level, const struct radeon_surf *surf, unsigned plane, unsigned layer) ac_surface_get_plane_offset() argument
2990 ac_surface_get_plane_stride(enum amd_gfx_level gfx_level, const struct radeon_surf *surf, unsigned plane, unsigned level) ac_surface_get_plane_stride() argument
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H A Dac_nir.h86 enum amd_gfx_level gfx_level,
104 enum amd_gfx_level gfx_level,
110 enum amd_gfx_level gfx_level,
115 enum amd_gfx_level gfx_level);
/third_party/mesa3d/src/amd/vulkan/winsys/null/
H A Dradv_null_winsys.c80 info->gfx_level = CLASS_UNKNOWN; in radv_null_winsys_query_info()
85 /* Override family and gfx_level. */ in radv_null_winsys_query_info()
90 info->gfx_level = GFX11; in radv_null_winsys_query_info()
92 info->gfx_level = GFX10_3; in radv_null_winsys_query_info()
94 info->gfx_level = GFX10; in radv_null_winsys_query_info()
96 info->gfx_level = GFX9; in radv_null_winsys_query_info()
98 info->gfx_level = GFX8; in radv_null_winsys_query_info()
100 info->gfx_level = GFX7; in radv_null_winsys_query_info()
102 info->gfx_level = GFX6; in radv_null_winsys_query_info()
114 if (info->gfx_level > in radv_null_winsys_query_info()
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/third_party/mesa3d/src/amd/vulkan/
H A Dsi_cmd_buffer.c49 if (physical_device->rad_info.gfx_level < GFX7) in si_write_harvested_raster_configs()
61 if (physical_device->rad_info.gfx_level < GFX7) in si_write_harvested_raster_configs()
70 if (physical_device->rad_info.gfx_level >= GFX7) in si_write_harvested_raster_configs()
93 if (device->physical_device->rad_info.gfx_level >= GFX7) { in si_emit_compute()
108 if (device->physical_device->rad_info.gfx_level >= GFX9 && in si_emit_compute()
109 device->physical_device->rad_info.gfx_level < GFX11) { in si_emit_compute()
111 device->physical_device->rad_info.gfx_level >= GFX10 ? 0x20 : 0); in si_emit_compute()
114 if (device->physical_device->rad_info.gfx_level >= GFX10) { in si_emit_compute()
128 if (device->physical_device->rad_info.gfx_level <= GFX6) { in si_emit_compute()
143 assert(device->physical_device->rad_info.gfx_level in si_emit_compute()
808 enum amd_gfx_level gfx_level = cmd_buffer->device->physical_device->rad_info.gfx_level; si_get_ia_multi_vgt_param() local
927 si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, bool is_mec, unsigned event, unsigned event_flags, unsigned dst_sel, unsigned data_sel, uint64_t va, uint32_t new_fence, uint64_t gfx9_eop_bug_va) si_cs_emit_write_event_eop() argument
1051 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, uint32_t *flush_cnt, uint64_t flush_va, bool is_mec, enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va) gfx10_cs_emit_cache_flush() argument
1232 si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, uint32_t *flush_cnt, uint64_t flush_va, bool is_mec, enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va) si_cs_emit_cache_flush() argument
1518 cp_dma_max_byte_count(enum amd_gfx_level gfx_level) cp_dma_max_byte_count() argument
1624 enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; si_cs_cp_dma_prefetch() local
1714 enum amd_gfx_level gfx_level = cmd_buffer->device->physical_device->rad_info.gfx_level; si_cp_dma_buffer_copy() local
1794 enum amd_gfx_level gfx_level = cmd_buffer->device->physical_device->rad_info.gfx_level; si_cp_dma_clear_buffer() local
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H A Dradv_debug.c87 ac_vm_fault_occured(device->physical_device->rad_info.gfx_level, &device->dmesg_timestamp, NULL); in radv_init_trace()
117 ac_dump_reg(f, device->physical_device->rad_info.gfx_level, offset, value, ~0); in radv_dump_mmapped_reg()
135 if (info->gfx_level <= GFX8) { in radv_dump_debug_registers()
154 radv_dump_buffer_descriptor(enum amd_gfx_level gfx_level, const uint32_t *desc, FILE *f) in radv_dump_buffer_descriptor() argument
158 ac_dump_reg(f, gfx_level, R_008F00_SQ_BUF_RSRC_WORD0 + j * 4, desc[j], 0xffffffff); in radv_dump_buffer_descriptor()
162 radv_dump_image_descriptor(enum amd_gfx_level gfx_level, const uint32_t *desc, FILE *f) in radv_dump_image_descriptor() argument
165 gfx_level >= GFX10 ? R_00A000_SQ_IMG_RSRC_WORD0 : R_008F10_SQ_IMG_RSRC_WORD0; in radv_dump_image_descriptor()
169 ac_dump_reg(f, gfx_level, sq_img_rsrc_word0 + j * 4, desc[j], 0xffffffff); in radv_dump_image_descriptor()
173 ac_dump_reg(f, gfx_level, sq_img_rsrc_word0 + j * 4, desc[8 + j], 0xffffffff); in radv_dump_image_descriptor()
177 radv_dump_sampler_descriptor(enum amd_gfx_level gfx_level, cons argument
186 radv_dump_combined_image_sampler_descriptor(enum amd_gfx_level gfx_level, const uint32_t *desc, FILE *f) radv_dump_combined_image_sampler_descriptor() argument
197 enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; radv_dump_descriptor_set() local
372 enum amd_gfx_level gfx_level = pipeline->device->physical_device->rad_info.gfx_level; radv_dump_annotated_shaders() local
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H A Dradv_sqtt.c54 if (device->physical_device->rad_info.gfx_level == GFX10_3) in gfx10_get_thread_trace_ctrl()
68 cs, device->physical_device->rad_info.gfx_level, NULL, 0, in radv_emit_wait_for_idle()
69 family == AMD_IP_COMPUTE && device->physical_device->rad_info.gfx_level >= GFX7, in radv_emit_wait_for_idle()
100 if (device->physical_device->rad_info.gfx_level >= GFX10) { in radv_emit_thread_trace_start()
152 if (device->physical_device->rad_info.gfx_level < GFX9) { in radv_emit_thread_trace_start()
171 if (device->physical_device->rad_info.gfx_level == GFX9) { in radv_emit_thread_trace_start()
183 if (device->physical_device->rad_info.gfx_level == GFX9) { in radv_emit_thread_trace_start()
230 if (device->physical_device->rad_info.gfx_level >= GFX10) { in radv_copy_thread_trace_info_regs()
232 } else if (device->physical_device->rad_info.gfx_level == GFX9) { in radv_copy_thread_trace_info_regs()
235 assert(device->physical_device->rad_info.gfx_level in radv_copy_thread_trace_info_regs()
[all...]
H A Dradv_image.c55 device->physical_device->rad_info.gfx_level <= GFX8) { in radv_choose_tiling()
73 if (device->physical_device->rad_info.gfx_level < GFX8) in radv_use_tc_compat_htile_for_image()
89 if (device->physical_device->rad_info.gfx_level < GFX9) { in radv_use_tc_compat_htile_for_image()
113 if (device->physical_device->rad_info.gfx_level >= GFX9) in radv_surface_has_scanout()
182 if (!radv_dcc_formats_compatible(pdev->rad_info.gfx_level, format, in radv_are_formats_dcc_compatible()
233 if (device->physical_device->rad_info.gfx_level < GFX8) in radv_use_dcc_for_image_early()
250 (device->physical_device->rad_info.gfx_level < GFX10 || in radv_use_dcc_for_image_early()
272 if (device->physical_device->rad_info.gfx_level < GFX10) { in radv_use_dcc_for_image_early()
279 device->physical_device->rad_info.gfx_level == GFX9) in radv_use_dcc_for_image_early()
321 return ac_surface_supports_dcc_image_stores(device->physical_device->rad_info.gfx_level, in radv_image_use_dcc_image_stores()
777 enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; si_set_mutable_tex_desc_fields() local
[all...]
H A Dradv_pipeline.c319 si_translate_blend_factor(enum amd_gfx_level gfx_level, VkBlendFactor factor) in si_translate_blend_factor() argument
343 return gfx_level >= GFX11 ? V_028780_BLEND_CONSTANT_COLOR_GFX11 in si_translate_blend_factor()
346 return gfx_level >= GFX11 ? V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR_GFX11 in si_translate_blend_factor()
349 return gfx_level >= GFX11 ? V_028780_BLEND_CONSTANT_ALPHA_GFX11 in si_translate_blend_factor()
352 return gfx_level >= GFX11 ? V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA_GFX11 in si_translate_blend_factor()
357 return gfx_level >= GFX11 ? V_028780_BLEND_SRC1_COLOR_GFX11 : V_028780_BLEND_SRC1_COLOR_GFX6; in si_translate_blend_factor()
359 return gfx_level >= GFX11 ? V_028780_BLEND_INV_SRC1_COLOR_GFX11 in si_translate_blend_factor()
362 return gfx_level >= GFX11 ? V_028780_BLEND_SRC1_ALPHA_GFX11 : V_028780_BLEND_SRC1_ALPHA_GFX6; in si_translate_blend_factor()
364 return gfx_level >= GFX11 ? V_028780_BLEND_INV_SRC1_ALPHA_GFX11 in si_translate_blend_factor()
447 is_dual_src(enum amd_gfx_level gfx_level, unsigne argument
642 radv_blend_check_commutativity(enum amd_gfx_level gfx_level, struct radv_blend_state *blend, unsigned op, unsigned src, unsigned dst, unsigned chanmask) radv_blend_check_commutativity() argument
700 const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; radv_pipeline_init_blend_state() local
2425 gfx10_emit_ge_pc_alloc(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, uint32_t oversub_pc_lines) gfx10_emit_ge_pc_alloc() argument
3703 enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level; radv_declare_pipeline_args() local
5014 radv_pipeline_stage_to_user_data_0(struct radv_graphics_pipeline *pipeline, gl_shader_stage stage, enum amd_gfx_level gfx_level) radv_pipeline_stage_to_user_data_0() argument
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/third_party/mesa3d/src/amd/compiler/
H A Daco_assembler.cpp45 enum amd_gfx_level gfx_level; member
51 asm_context(Program* program_) : program(program_), gfx_level(program->gfx_level) in asm_context()
53 if (gfx_level <= GFX7) in asm_context()
55 else if (gfx_level <= GFX9) in asm_context()
57 else if (gfx_level >= GFX10) in asm_context()
126 assert(ctx.gfx_level >= GFX10); in emit_instruction()
130 assert(ctx.gfx_level >= GFX10); in emit_instruction()
184 if (ctx.gfx_level <= GFX7) { in emit_instruction()
207 if (ctx.gfx_level < in emit_instruction()
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H A Daco_ir.cpp69 enum amd_gfx_level gfx_level, enum radeon_family family, bool wgp_mode, in init_program()
75 program->gfx_level = gfx_level; in init_program()
77 switch (gfx_level) { in init_program()
91 program->dev.lds_encoding_granule = gfx_level >= GFX11 && stage == fragment_fs ? 1024 : in init_program()
92 gfx_level >= GFX7 ? 512 : 256; in init_program()
93 program->dev.lds_alloc_granule = gfx_level >= GFX10_3 ? 1024 : program->dev.lds_encoding_granule; in init_program()
94 program->dev.lds_limit = gfx_level >= GFX7 ? 65536 : 32768; in init_program()
102 if (gfx_level >= GFX10) { in init_program()
108 if (gfx_level in init_program()
68 init_program(Program* program, Stage stage, const struct aco_shader_info* info, enum amd_gfx_level gfx_level, enum radeon_family family, bool wgp_mode, ac_shader_config* config) init_program() argument
203 can_use_SDWA(amd_gfx_level gfx_level, const aco_ptr<Instruction>& instr, bool pre_ra) can_use_SDWA() argument
269 convert_to_SDWA(amd_gfx_level gfx_level, aco_ptr<Instruction>& instr) convert_to_SDWA() argument
403 can_use_opsel(amd_gfx_level gfx_level, aco_opcode op, int idx) can_use_opsel() argument
446 instr_is_16bit(amd_gfx_level gfx_level, aco_opcode op) instr_is_16bit() argument
815 wait_imm(enum amd_gfx_level gfx_level, uint16_t packed) wait_imm() argument
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H A Daco_print_asm.cpp103 to_clrx_device_name(amd_gfx_level gfx_level, radeon_family family) in to_clrx_device_name() argument
105 switch (gfx_level) { in to_clrx_device_name()
185 const char* gpu_type = to_clrx_device_name(program->gfx_level, program->family); in print_asm_clrx()
271 disasm_instr(amd_gfx_level gfx_level, LLVMDisasmContextRef disasm, uint32_t* binary, in disasm_instr() argument
278 if (gfx_level >= GFX10 && l == 8 && ((binary[pos] & 0xffff0000) == 0xd7610000) && in disasm_instr()
287 ((gfx_level >= GFX9 && in disasm_instr()
289 (gfx_level >= GFX10 && in disasm_instr()
291 (gfx_level <= GFX9 && in disasm_instr()
293 (gfx_level >= GFX10 && (binary[pos] & 0xffff8000) == 0xd76d8000) || /* v_add3_u32 + clamp */ in disasm_instr()
294 (gfx_level in disasm_instr()
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/third_party/mesa3d/src/amd/registers/
H A Dparse_kernel_headers.py71 def register_filter(gfx_level, name, offset, already_added):
84 (gfx_level == 'gfx6' and offset // 0x1000 == 0x8) or
693 def generate_json(gfx_level, amd_headers_path):
694 gc_base_offsets = gfx_levels[gfx_level][0]
697 filenames = [amd_headers_path + '/' + a for a in gfx_levels[gfx_level][1:]]
730 if register_filter(gfx_level, name, offset, offset in added_offsets):
732 'chips': [gfx_level],
769 enums = enums_missing[gfx_level] if gfx_level in enums_missing else {}
799 missing_fields = fields_missing[gfx_level] i
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/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_state.c106 if (sctx->gfx_level >= GFX8) { in si_emit_cb_render_state()
114 if (sctx->gfx_level >= GFX11) { in si_emit_cb_render_state()
121 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx->gfx_level <= GFX9) | in si_emit_cb_render_state()
122 S_028424_OVERWRITE_COMBINER_WATERMARK(sctx->gfx_level >= GFX10 ? 6 : 4) | in si_emit_cb_render_state()
124 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->gfx_level < GFX11 && in si_emit_cb_render_state()
153 format = sctx->gfx_level >= GFX11 ? G_028C70_FORMAT_GFX11(surf->cb_color_info): in si_emit_cb_render_state()
160 has_alpha = !(sctx->gfx_level >= GFX11 ? G_028C74_FORCE_DST_ALPHA_1_GFX11(surf->cb_color_attrib): in si_emit_cb_render_state()
300 static uint32_t si_translate_blend_factor(enum amd_gfx_level gfx_level, int blend_fact) in si_translate_blend_factor() argument
316 return gfx_level >= GFX11 ? V_028780_BLEND_CONSTANT_COLOR_GFX11: in si_translate_blend_factor()
319 return gfx_level > in si_translate_blend_factor()
1658 si_translate_colorformat(enum amd_gfx_level gfx_level, enum pipe_format format) si_translate_colorformat() argument
2384 si_is_colorbuffer_format_supported(enum amd_gfx_level gfx_level, enum pipe_format format) si_is_colorbuffer_format_supported() argument
[all...]
H A Dsi_get.c52 bool enable_sparse = sscreen->info.gfx_level >= GFX9 && in si_get_param()
180 return sscreen->info.gfx_level < GFX11; in si_get_param()
192 return sscreen->info.gfx_level >= GFX10; in si_get_param()
238 if (sscreen->info.gfx_level <= GFX8) in si_get_param()
307 return sscreen->info.gfx_level <= GFX8 ? PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0; in si_get_param()
339 if (sscreen->info.gfx_level >= GFX10) in si_get_param()
344 if (sscreen->info.gfx_level >= GFX10) in si_get_param()
501 return sscreen->info.gfx_level >= GFX8 && sscreen->options.fp16; in si_get_shader_param()
638 if (sscreen->info.gfx_level >= GFX11) in si_get_video_param()
643 if (sscreen->info.gfx_level > in si_get_video_param()
[all...]
H A Dsi_state_shaders.cpp46 if (sscreen->info.gfx_level < GFX10) in si_determine_wave_size()
121 !(sscreen->info.gfx_level == GFX10 && shader && shader->key.ge.opt.ngg_culling)) in si_determine_wave_size()
504 if (shader->selector->screen->info.gfx_level < GFX10) in si_shader_mem_ordered()
591 if (sscreen->info.family < CHIP_POLARIS10 || sscreen->info.gfx_level >= GFX10) in polaris_set_vgt_vertex_reuse()
649 if (sscreen->info.gfx_level >= GFX10) in si_get_vs_vgpr_comp_cnt()
663 if (is_ls && sscreen->info.gfx_level <= GFX10_3) in si_get_vs_vgpr_comp_cnt()
688 assert(sscreen->info.gfx_level <= GFX8); in si_shader_ls()
717 if (sscreen->info.gfx_level >= GFX9) { in si_shader_hs()
718 if (sscreen->info.gfx_level >= GFX11) { in si_shader_hs()
725 if (sscreen->info.gfx_level > in si_shader_hs()
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H A Dsi_build_pm4.h154 #define radeon_set_uconfig_reg_idx(screen, gfx_level, reg, idx, value) do { \
159 if ((gfx_level) < GFX9 || \
160 ((gfx_level) == GFX9 && (screen)->info.me_fw_version < 26)) \
266 if (sctx->gfx_level >= GFX10) \
326 si_get_user_data_base(enum amd_gfx_level gfx_level, enum si_has_tess has_tess, in si_get_user_data_base() argument
334 if (gfx_level >= GFX10) { in si_get_user_data_base()
336 } else if (gfx_level == GFX9) { in si_get_user_data_base()
341 } else if (gfx_level >= GFX10) { in si_get_user_data_base()
354 if (gfx_level == GFX9) { in si_get_user_data_base()
363 if (gfx_level > in si_get_user_data_base()
[all...]
H A Dsi_compute.c158 if (sscreen->info.gfx_level < GFX11) in si_create_compute_state_async()
203 S_00B848_WGP_MODE(sscreen->info.gfx_level >= GFX10) | in si_create_compute_state_async()
206 if (sscreen->info.gfx_level < GFX10) { in si_create_compute_state_async()
388 if (sctx->gfx_level == GFX6) { in si_emit_initial_compute_regs()
400 if (sctx->gfx_level >= GFX7) { in si_emit_initial_compute_regs()
426 if (sctx->gfx_level >= GFX9 && sctx->gfx_level < GFX11 && in si_emit_initial_compute_regs()
429 sctx->gfx_level >= GFX10 ? 0x20 : 0); in si_emit_initial_compute_regs()
440 if (sctx->gfx_level >= GFX10) { in si_emit_initial_compute_regs()
449 if (sctx->gfx_level < GFX1 in si_emit_initial_compute_regs()
[all...]
/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_hw_context.c76 if (ctx->b.gfx_level == R600) { in r600_need_cs_space()
142 if (rctx->b.gfx_level >= R700 && in r600_flush_emit()
148 if (rctx->b.gfx_level >= R700 && in r600_flush_emit()
163 (rctx->b.gfx_level == R600 && rctx->b.flags & R600_CONTEXT_STREAMOUT_FLUSH)) { in r600_flush_emit()
189 if (rctx->b.gfx_level >= R700 && in r600_flush_emit()
199 if (rctx->b.gfx_level >= R700 && in r600_flush_emit()
211 if (rctx->b.gfx_level >= EVERGREEN) in r600_flush_emit()
218 if (rctx->b.gfx_level >= R700 && in r600_flush_emit()
288 if (ctx->b.gfx_level == R600) { in r600_context_gfx_flush()
359 if (ctx->b.gfx_level > in r600_begin_new_cs()
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