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Searched refs:fneg (Results 1 - 25 of 42) sorted by relevance

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/third_party/mesa3d/src/amd/compiler/tests/
H A Dtest_optimizer.cpp36 Temp neg_b = fneg(inputs[1]);
43 Temp neg_a = fneg(inputs[0]);
48 Temp neg_neg_a = fneg(neg_a);
59 Temp neg_abs_a = fneg(abs_a);
76 Temp neg_c = fneg(bld.copy(bld.def(v1), inputs[2]));
723 Temp xor0 = fneg(inputs[0]);
725 Temp xor1 = fneg(min);
731 xor1 = fneg(min);
827 "fneg",
908 //; 'fneg'
[all...]
H A Dtest_sdwa.cpp289 Temp neg_byte0 = fneg(byte0);
297 Temp neg = fneg(inputs[1]);
317 Temp neg_abs_byte0 = fneg(abs_byte0);
325 Temp neg_abs = fneg(abs);
H A Dhelpers.h94 aco::Temp fneg(aco::Temp src, aco::Builder b=bld);
H A Dhelpers.cpp271 Temp fneg(Temp src, Builder b) in fneg() function
/third_party/ffmpeg/libavcodec/aarch64/
H A Dmdct_neon.S155 fneg v4.4s, v0.4s
231 fneg v7.2s, v7.2s // R*s-I*c
258 fneg v7.2s, v7.2s // R*s-I*c
309 fneg v4.2s, v4.2s
310 fneg v6.2s, v6.2s
H A Daacpsdsp_neon.S72 fneg v2.4S, v1.4S
73 fneg v3.4S, v7.4S
H A Dfft_neon.S191 fneg v22.4s, v20.4s
216 fneg v26.4s, v24.4s
281 fneg v22.4s, v20.4s
319 fneg v22.4s, v20.4s
/third_party/ltp/tools/sparse/sparse-src/validation/
H A Dfp-ops.c5 double fneg(double x) { return -x; } in fneg() function
41 fneg:
44 fneg.64 %r18 <- %arg1
/third_party/vixl/test/aarch64/
H A Dtest-disasm-fp-aarch64.cc76 COMPARE(fneg(s4, s5), "fneg s4, s5"); in TEST()
77 COMPARE(fneg(s31, s30), "fneg s31, s30"); in TEST()
78 COMPARE(fneg(d6, d7), "fneg d6, d7"); in TEST()
79 COMPARE(fneg(d31, d30), "fneg d31, d30"); in TEST()
H A Dtest-cpu-features-aarch64.cc627 TEST_FP(fneg_0, fneg(d0, d1))
628 TEST_FP(fneg_1, fneg(s0, s1))
3317 TEST_FP_NEON(fneg_0, fneg(v0.V2S(), v1.V2S()))
3318 TEST_FP_NEON(fneg_1, fneg(v0.V4S(), v1.V4S()))
3319 TEST_FP_NEON(fneg_2, fneg(v0.V2D(), v1.V2D()))
3495 TEST_FP_FPHALF(fneg_0, fneg(h0, h1))
3699 TEST_FP_NEON_NEONHALF(fneg_0, fneg(v0.V4H(), v1.V4H()))
3700 TEST_FP_NEON_NEONHALF(fneg_1, fneg(v0.V8H(), v1.V8H()))
H A Dtest-trace-aarch64.cc556 __ fneg(d15, d0); in GenerateTestSequenceFP()
557 __ fneg(s14, s15); in GenerateTestSequenceFP()
2696 __ fneg(v1.V2D(), v25.V2D()); in GenerateTestSequenceNEONFP()
2697 __ fneg(v14.V2S(), v31.V2S()); in GenerateTestSequenceNEONFP()
2698 __ fneg(v5.V4S(), v4.V4S()); in GenerateTestSequenceNEONFP()
/third_party/ltp/tools/sparse/sparse-src/validation/backend/
H A Darithmetic-ops.c101 static float fneg(float x) in fneg() function
/third_party/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_compiler_nir_emit.c65 OP(mov, MOV, X_X_0), OP(fneg, MOV, X_X_0), OP(fabs, MOV, X_X_0), OP(fsat, MOV, X_X_0),
/third_party/mesa3d/src/amd/compiler/
H A Daco_optimizer.cpp3468 /* check for fneg modifiers */ in combine_vop3p()
3479 VOP3P_instruction* fneg = &info.instr->vop3p(); in combine_vop3p() local
3481 if ((fneg->opsel_lo | fneg->opsel_hi) & 2) in combine_vop3p()
3491 if (fneg->clamp) in combine_vop3p()
3493 instr->operands[i] = fneg->operands[0]; in combine_vop3p()
3496 * if 0 - pick selection from fneg->lo in combine_vop3p()
3497 * if 1 - pick selection from fneg->hi in combine_vop3p()
3501 bool neg_lo = fneg->neg_lo[0] ^ fneg in combine_vop3p()
[all...]
/third_party/node/deps/v8/src/diagnostics/loong64/
H A Ddisasm-loong64.cc1423 Format(instr, "fneg.s 'fd, 'fj"); in DecodeTypekOp22()
1426 Format(instr, "fneg.d 'fd, 'fj"); in DecodeTypekOp22()
/third_party/node/deps/v8/src/diagnostics/ppc/
H A Ddisasm-ppc.cc1439 Format(instr, "fneg'. 'Dt, 'Db"); in DecodeExt4()
/third_party/node/deps/v8/src/diagnostics/riscv64/
H A Ddisasm-riscv64.cc1102 Format(instr, "fneg.s 'fd, 'fs1"); in DecodeRFPType()
1244 Format(instr, "fneg.d 'fd, 'fs1"); in DecodeRFPType()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/AsmParser/
H A DLLLexer.cpp841 INSTKEYWORD(fneg, FNeg); in LexIdentifier()
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-logic-arm64.cc3282 return fneg(vform, dst, product); in fnmul()
3532 LogicVRegister Simulator::fneg(VectorFormat vform, LogicVRegister dst, in fneg() function in v8::internal::Simulator
3543 LogicVRegister Simulator::fneg(VectorFormat vform, LogicVRegister dst, in fneg() function in v8::internal::Simulator
3546 fneg<float>(vform, dst, src); in fneg()
3549 fneg<double>(vform, dst, src); in fneg()
H A Dsimulator-arm64.h2113 LogicVRegister fneg(VectorFormat vform, LogicVRegister dst,
2115 LogicVRegister fneg(VectorFormat vform, LogicVRegister dst,
/third_party/vixl/src/aarch64/
H A Dlogic-aarch64.cc5042 return fneg(vform, dst, product);
5439 LogicVRegister Simulator::fneg(VectorFormat vform,
5452 LogicVRegister Simulator::fneg(VectorFormat vform,
5456 fneg<SimFloat16>(vform, dst, src);
5458 fneg<float>(vform, dst, src);
5461 fneg<double>(vform, dst, src);
H A Dsimulator-aarch64.cc6374 fneg(vform, ReadVRegister(fd), ReadVRegister(fn)); in Simulator()
7055 fneg(fpf, rd, rn); in Simulator()
7296 fneg(fpf, rd, rn); in Simulator()
10604 fneg(vform, result, zd); in Simulator()
10613 fneg(vform, result, zd); in Simulator()
10632 fneg(vform, result, za); in Simulator()
10641 fneg(vform, result, za); in Simulator()
11724 fneg(vform, result, zn); in Simulator()
/third_party/node/deps/v8/src/wasm/baseline/ppc/
H A Dliftoff-assembler-ppc.h1094 V(f32_neg, fneg, DoubleRegister, DoubleRegister, , , USE, , void) \
1104 V(f64_neg, fneg, DoubleRegister, DoubleRegister, , , USE, , void) \
/third_party/node/deps/v8/src/codegen/ppc/
H A Dassembler-ppc.h1098 void fneg(const DoubleRegister frt, const DoubleRegister frb,
H A Dmacro-assembler-ppc.cc1829 fneg(scratch, lhs); in CallRecordWriteStub()
1835 fneg(dst, dst); in CallRecordWriteStub()

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