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Searched refs:dispatch_mode (Results 1 - 16 of 16) sorted by relevance

/third_party/mesa3d/src/intel/compiler/
H A Dbrw_vec4_gs_visitor.cpp134 prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT ? 1 : 2; in setup_payload()
825 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8; in brw_compile_gs()
855 prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT; in brw_compile_gs()
919 prog_data->base.dispatch_mode = DISPATCH_MODE_4X1_SINGLE; in brw_compile_gs()
921 prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_INSTANCE; in brw_compile_gs()
H A Dbrw_vec4.cpp1847 enum shader_dispatch_mode dispatch_mode) in stage_uses_interleaved_attributes()
1853 return dispatch_mode != DISPATCH_MODE_4X2_DUAL_OBJECT; in stage_uses_interleaved_attributes()
1867 enum shader_dispatch_mode dispatch_mode, in get_lowered_simd_width()
1909 stage_uses_interleaved_attributes(stage, dispatch_mode)) in get_lowered_simd_width()
1963 get_lowered_simd_width(devinfo, prog_data->dispatch_mode, stage, inst); in lower_simd_width()
2021 prog_data->dispatch_mode); in lower_simd_width()
2119 (stage_uses_interleaved_attributes(stage, prog_data->dispatch_mode) && in is_supported_64bit_region()
2635 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8; in brw_compile_vs()
2666 prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT; in brw_compile_vs()
1846 stage_uses_interleaved_attributes(unsigned stage, enum shader_dispatch_mode dispatch_mode) stage_uses_interleaved_attributes() argument
1866 get_lowered_simd_width(const struct intel_device_info *devinfo, enum shader_dispatch_mode dispatch_mode, unsigned stage, const vec4_instruction *inst) get_lowered_simd_width() argument
H A Dtest_vec4_dead_code_eliminate.cpp53 prog_data->dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT; in dead_code_eliminate_vec4_visitor()
H A Dtest_vec4_copy_propagation.cpp53 prog_data->dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT; in copy_propagation_vec4_visitor()
H A Dbrw_vec4_tcs.cpp406 vue_prog_data->dispatch_mode = DISPATCH_MODE_TCS_8_PATCH; in brw_compile_tcs()
411 vue_prog_data->dispatch_mode = DISPATCH_MODE_TCS_SINGLE_PATCH; in brw_compile_tcs()
H A Dtest_vec4_register_coalesce.cpp56 prog_data->dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT; in register_coalesce_vec4_visitor()
H A Dbrw_vec4_copy_propagation.cpp466 prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT ? 1 : 2; in opt_copy_propagation()
H A Dbrw_compiler.h1312 enum shader_dispatch_mode dispatch_mode; member
H A Dbrw_shader.cpp1426 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8; in brw_compile_tes()
H A Dbrw_fs.cpp6679 if (vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_8_PATCH) {
6685 assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH);
6710 assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH ||
6711 vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_8_PATCH);
6713 if (vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH) {
6717 assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_8_PATCH);
6730 vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH &&
H A Dtest_vec4_cmod_propagation.cpp57 prog_data->dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT; in cmod_propagation_vec4_visitor()
H A Dbrw_fs_nir.cpp2828 if (vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH) {
2831 assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_8_PATCH);
2846 vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_8_PATCH;
/third_party/mesa3d/src/intel/vulkan/
H A DgenX_pipeline.c1530 vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8; in emit_3dstate_vs()
1663 hs.DispatchMode = tcs_prog_data->base.dispatch_mode; in emit_3dstate_hs_te_ds()
1720 tes_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8 ? in emit_3dstate_hs_te_ds()
1724 assert(tes_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8); in emit_3dstate_hs_te_ds()
1766 gs.DispatchMode = gs_prog_data->base.dispatch_mode; in emit_3dstate_gs()
/third_party/mesa3d/src/intel/blorp/
H A Dblorp_genX_exec.h694 vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8); in blorp_emit_vs_config()
713 vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8; in blorp_emit_vs_config()
/third_party/mesa3d/src/gallium/drivers/crocus/
H A Dcrocus_state.c6801 vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8;
6866 gs.DispatchMode = vue_prog_data->dispatch_mode;
7035 if (vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8)
/third_party/mesa3d/src/gallium/drivers/iris/
H A Diris_state.c4563 hs.DispatchMode = vue_prog_data->dispatch_mode; in iris_store_tcs_state()

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