| /third_party/elfutils/libdwfl/ |
| H A D | linux-core-attach.c | 106 size_t desc_offset; in core_next_thread() local
129 &desc_offset)) > 0) in core_next_thread()
134 const char *desc = note_data->d_buf + desc_offset; in core_next_thread()
176 size_t desc_offset; in core_set_initial_registers() local
182 &desc_offset); in core_set_initial_registers()
189 const char *desc = note_data->d_buf + desc_offset; in core_set_initial_registers()
374 size_t desc_offset; in dwfl_core_file_attach() local
377 &nhdr, &name_offset, &desc_offset)) > 0) in dwfl_core_file_attach()
382 const char *desc = note_data->d_buf + desc_offset; in dwfl_core_file_attach()
|
| /third_party/mesa3d/src/intel/vulkan/ |
| H A D | anv_nir_apply_pipeline_layout.c | 56 uint8_t desc_offset; member
207 surface_index = state->set[set].desc_offset; in descriptor_has_bti()
249 nir_ssa_def *desc_addr, unsigned desc_offset, in build_load_descriptor_mem()
259 nir_iadd_imm(b, nir_channel(b, desc_addr, 3), desc_offset); in build_load_descriptor_mem()
264 .align_offset = desc_offset % 8); in build_load_descriptor_mem()
270 nir_iadd_imm(b, nir_channel(b, desc_addr, 1), desc_offset); in build_load_descriptor_mem()
275 .align_offset = desc_offset % 8, in build_load_descriptor_mem()
325 assert(state->set[set].desc_offset < MAX_BINDING_TABLE_SIZE); in build_res_index()
326 set_idx = state->set[set].desc_offset; in build_res_index()
352 uint32_t surface_index = state->set[set].desc_offset; in build_res_index()
248 build_load_descriptor_mem(nir_builder *b, nir_ssa_def *desc_addr, unsigned desc_offset, unsigned num_components, unsigned bit_size, struct apply_pipeline_layout_state *state) build_load_descriptor_mem() argument
445 nir_ssa_def *desc_offset = res.desc_offset_base; build_desc_addr() local
570 build_load_var_deref_descriptor_mem(nir_builder *b, nir_deref_instr *deref, unsigned desc_offset, unsigned num_components, unsigned bit_size, struct apply_pipeline_layout_state *state) build_load_var_deref_descriptor_mem() argument
[all...] |
| /third_party/elfutils/libelf/ |
| H A D | gelf_getnote.c | 41 size_t *name_offset, size_t *desc_offset) in gelf_getnote()
78 And normally desc_offset is also 4 byte aligned, but not in gelf_getnote()
105 *desc_offset = offset; in gelf_getnote()
40 gelf_getnote(Elf_Data *data, size_t offset, GElf_Nhdr *result, size_t *name_offset, size_t *desc_offset) gelf_getnote() argument
|
| /third_party/elfutils/src/ |
| H A D | elfcmp.c | 431 size_t desc_offset; in main() local
434 &name_offset, &desc_offset)) > 0) in main()
438 const void *desc1 = data1->d_buf + desc_offset; in main()
448 &name_offset, &desc_offset); in main()
455 const void *desc2 = data2->d_buf + desc_offset; in main()
|
| H A D | readelf.c | 12686 size_t desc_offset; in handle_notes_data() local
12689 &nhdr, &name_offset, &desc_offset)) > 0) in handle_notes_data()
12692 const char *desc = data->d_buf + desc_offset; in handle_notes_data()
12727 start + desc_offset); in handle_notes_data()
12733 start + desc_offset); in handle_notes_data()
12738 start + desc_offset); in handle_notes_data()
|
| H A D | elflint.c | 4312 size_t desc_offset; in check_note_data() local
4315 &nhdr, &name_offset, &desc_offset)) > 0) in check_note_data()
|
| /third_party/mesa3d/src/freedreno/vulkan/ |
| H A D | tu_shader.c | 358 nir_ssa_def *desc_offset; in build_bindless() local
368 desc_offset = in build_bindless()
377 desc_offset = nir_iadd(b, desc_offset, in build_bindless()
381 return nir_bindless_resource_ir3(b, 32, desc_offset, .desc_set = set); in build_bindless()
|
| /third_party/mesa3d/src/microsoft/vulkan/ |
| H A D | dzn_descriptor_set.c | 839 dzn_descriptor_heap_get_cpu_handle(const struct dzn_descriptor_heap *heap, uint32_t desc_offset) in dzn_descriptor_heap_get_cpu_handle() argument
842 .ptr = heap->cpu_base + (desc_offset * heap->desc_sz), in dzn_descriptor_heap_get_cpu_handle()
847 dzn_descriptor_heap_get_gpu_handle(const struct dzn_descriptor_heap *heap, uint32_t desc_offset) in dzn_descriptor_heap_get_gpu_handle() argument
850 .ptr = heap->gpu_base ? heap->gpu_base + (desc_offset * heap->desc_sz) : 0, in dzn_descriptor_heap_get_gpu_handle()
856 uint32_t desc_offset, in dzn_descriptor_heap_write_sampler_desc()
860 dzn_descriptor_heap_get_cpu_handle(heap, desc_offset)); in dzn_descriptor_heap_write_sampler_desc()
865 uint32_t desc_offset, in dzn_descriptor_heap_write_image_view_desc()
870 dzn_descriptor_heap_get_cpu_handle(heap, desc_offset); in dzn_descriptor_heap_write_image_view_desc()
907 uint32_t desc_offset, in dzn_descriptor_heap_write_buffer_view_desc()
912 dzn_descriptor_heap_get_cpu_handle(heap, desc_offset); in dzn_descriptor_heap_write_buffer_view_desc()
855 dzn_descriptor_heap_write_sampler_desc(struct dzn_descriptor_heap *heap, uint32_t desc_offset, const struct dzn_sampler *sampler) dzn_descriptor_heap_write_sampler_desc() argument
864 dzn_descriptor_heap_write_image_view_desc(struct dzn_descriptor_heap *heap, uint32_t desc_offset, bool writeable, bool cube_as_2darray, const struct dzn_image_view *iview) dzn_descriptor_heap_write_image_view_desc() argument
906 dzn_descriptor_heap_write_buffer_view_desc(struct dzn_descriptor_heap *heap, uint32_t desc_offset, bool writeable, const struct dzn_buffer_view *bview) dzn_descriptor_heap_write_buffer_view_desc() argument
921 dzn_descriptor_heap_write_buffer_desc(struct dzn_descriptor_heap *heap, uint32_t desc_offset, bool writeable, const struct dzn_buffer_desc *info) dzn_descriptor_heap_write_buffer_desc() argument
[all...] |
| /third_party/mesa3d/src/panfrost/vulkan/ |
| H A D | panvk_vX_nir_lower_descriptors.c | 355 unsigned desc_offset, in load_resource_deref_desc()
380 bind_layout->desc_ubo_offset + desc_offset); in load_resource_deref_desc()
390 .align_offset=(desc_offset % desc_align), in load_resource_deref_desc()
354 load_resource_deref_desc(nir_builder *b, nir_deref_instr *deref, unsigned desc_offset, unsigned num_components, unsigned bit_size, const struct apply_descriptors_ctx *ctx) load_resource_deref_desc() argument
|
| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| H A D | si_descriptors.c | 2293 unsigned desc_offset = si_get_image_slot(i) * 8; in si_emit_compute_shader_pointers() local
2298 desc_offset += 4; in si_emit_compute_shader_pointers()
2302 radeon_emit_array(&desc->list[desc_offset], num_sgprs); in si_emit_compute_shader_pointers()
|