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Searched refs:coherent_seqnos (Results 1 - 3 of 3) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/iris/
H A D	iris_batch.h	156 * coherent_seqnos[i][j] denotes the seqno of the most recent flush of 158 * coherent_seqnos[i][i] is the most recent flush of cache domain i). This 163 uint64_t coherent_seqnos[NUM_IRIS_DOMAINS][NUM_IRIS_DOMAINS]; member 366 batch->coherent_seqnos[access][access] = batch->next_seqno - 1; in iris_batch_mark_flush_sync() 392 batch->coherent_seqnos[access][i] = in iris_batch_mark_invalidate_sync() 394 batch->l3_coherent_seqnos[i] : batch->coherent_seqnos[i][i]; in iris_batch_mark_invalidate_sync() 401 batch->coherent_seqnos[access][i] = batch->l3_coherent_seqnos[i]; in iris_batch_mark_invalidate_sync() 407 batch->coherent_seqnos[access][i] = batch->coherent_seqnos[i][i]; in iris_batch_mark_invalidate_sync() 423 batch->coherent_seqnos[ in iris_batch_mark_reset_sync() [all...]
H A D	iris_pipe_control.c	180 * have for the local seqno (see the coherent_seqnos comparisons below). 243 if (seqno > batch->coherent_seqnos[access][i]) { in iris_emit_buffer_barrier_for() 256 if (seqno > batch->coherent_seqnos[i][i]) in iris_emit_buffer_barrier_for() 275 batch->l3_coherent_seqnos[i] : batch->coherent_seqnos[i][i]; in iris_emit_buffer_barrier_for() 300 if (seqno > batch->coherent_seqnos[access][i]) { in iris_emit_buffer_barrier_for() 311 if (seqno > batch->coherent_seqnos[i][i]) in iris_emit_buffer_barrier_for()
H A D	iris_state.c	`7631 batch->coherent_seqnos[c][c] = batch->l3_coherent_seqnos[c]; in batch_mark_sync_for_pipe_control() 7632 batch->coherent_seqnos[z][z] = batch->l3_coherent_seqnos[z]; in batch_mark_sync_for_pipe_control() 7643 batch->coherent_seqnos[i][i] = batch->l3_coherent_seqnos[i]; in batch_mark_sync_for_pipe_control() 7701 batch->l3_coherent_seqnos[i] = batch->coherent_seqnos[i][i]; in batch_mark_sync_for_pipe_control()`

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