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Searched refs:Q4 (Results 1 - 21 of 21) sorted by relevance

/third_party/jerryscript/jerry-libm/
H A Dexpm1.c55 * R1(z) ~ 1.0 + Q1*z + Q2*z**2 + Q3*z**3 + Q4*z**4 + Q5*z**5
59 * Q4 = 2.5051361420808517002E-7,
136 #define Q4 4.00821782732936239552e-06 /* 3ED0CFCA 86E65239 */ macro
233 r1 = one + hxs * (Q1 + hxs * (Q2 + hxs * (Q3 + hxs * (Q4 + hxs * Q5)))); in expm1()
304 #undef Q4 macro
/third_party/ffmpeg/libavcodec/x86/
H A Dvp9lpf.asm330 %define Q4 dst2q + %1
350 %define Q4 rsp + 12*mmsize + %1
429 movx m12, [Q4]
468 mova [Q4], m12
482 movh [Q4], m6
496 movx m4, [Q4]
506 movh [Q4], m6
527 movx m3, [Q4]
736 mova m14, [Q4]
741 %define rq4 [Q4]
[all...]
/third_party/musl/porting/liteos_a/kernel/src/math/
H A Dexpm1l.c72 Q4 = -4.002027679107076077238836622982900945173E1L, variable
106 qx = (((( x + Q4) * x + Q3) * x + Q2) * x + Q1) * x + Q0; in expm1l()
H A Dexpm1.c38 * R1(z) ~ 1.0 + Q1*z + Q2*z**2 + Q3*z**3 + Q4*z**4 + Q5*z**5
42 * Q4 = 2.5051361420808517002E-7,
118 Q4 = 4.00821782732936239552e-06, /* 3ED0CFCA 86E65239 */ variable
170 r1 = 1.0+hxs*(Q1+hxs*(Q2+hxs*(Q3+hxs*(Q4+hxs*Q5)))); in expm1()
/third_party/musl/src/math/
H A Dexpm1l.c72 Q4 = -4.002027679107076077238836622982900945173E1L, variable
106 qx = (((( x + Q4) * x + Q3) * x + Q2) * x + Q1) * x + Q0; in expm1l()
H A Dexpm1.c38 * R1(z) ~ 1.0 + Q1*z + Q2*z**2 + Q3*z**3 + Q4*z**4 + Q5*z**5
42 * Q4 = 2.5051361420808517002E-7,
118 Q4 = 4.00821782732936239552e-06, /* 3ED0CFCA 86E65239 */ variable
170 r1 = 1.0+hxs*(Q1+hxs*(Q2+hxs*(Q3+hxs*(Q4+hxs*Q5)))); in expm1()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp36 AArch64::Q3, AArch64::Q4, AArch64::Q5,
H A DAArch64PBQPRegAlloc.cpp130 case AArch64::Q4: in isOdd()
H A DAArch64FastISel.cpp3017 { AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, in fastLowerArguments()
H A DAArch64ISelLowering.cpp3639 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7}; in saveVarArgRegisters()
/third_party/mesa3d/src/mesa/main/
H A Dtexcompress_astc.cpp173 uint8_t Q4 = (in >> (2*n+4)) & 0x1; in unpack_quint_block() local
184 q2 = CAT_BITS_3(Q0, Q4 & ~Q0, Q3 & ~Q0); in unpack_quint_block()
190 C = CAT_BITS_5(Q4, Q3, 0x1 & ~Q6, 0x1 & ~Q5, Q0); in unpack_quint_block()
193 C = CAT_BITS_5(Q4, Q3, Q2, Q1, Q0); in unpack_quint_block()
/third_party/typescript/tests/baselines/reference/
H A DconditionalTypes1.js180 type Q4 = IsString<never>; // never
600 type Q4 = IsString<never>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp199 {codeview::RegisterId::ARM64_Q4, AArch64::Q4}, in initLLVMToCVRegMapping()
H A DAArch64InstPrinter.cpp1168 case AArch64::Q3: Reg = AArch64::Q4; break; in getNextVectorRegister()
1169 case AArch64::Q4: Reg = AArch64::Q5; break; in getNextVectorRegister()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp95 SP::Q4, SP::Q12, ~0U, ~0U,
/third_party/node/deps/v8/src/base/
H A Dieee754.cc2141 * R1(z) ~ 1.0 + Q1*z + Q2*z**2 + Q3*z**3 + Q4*z**4 + Q5*z**5
2145 * Q4 = 2.5051361420808517002E-7,
2222 Q4 = 4.00821782732936239552e-06, /* 3ED0CFCA 86E65239 */ in expm1() local
2284 r1 = one + hxs * (Q1 + hxs * (Q2 + hxs * (Q3 + hxs * (Q4 + hxs * Q5)))); in expm1()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp305 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
629 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp580 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: in getMachineOpValue()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp160 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1365 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1383 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp2094 .Case("v4", AArch64::Q4) in MatchNeonVectorRegName()

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