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Searched refs:PIPE_CONTROL_CACHE_INVALIDATE_BITS (Results 1 - 5 of 5) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/crocus/
H A Dcrocus_pipe_control.c66 (flags & PIPE_CONTROL_CACHE_INVALIDATE_BITS)) { in crocus_emit_pipe_control_flush()
H A Dcrocus_context.h267 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS \ macro
/third_party/mesa3d/src/gallium/drivers/iris/
H A Diris_pipe_control.c63 (flags & PIPE_CONTROL_CACHE_INVALIDATE_BITS)) { in iris_emit_pipe_control_flush()
H A Diris_context.h370 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS \ macro
H A Diris_state.c8146 (flags & (PIPE_CONTROL_CACHE_FLUSH_BITS | PIPE_CONTROL_CACHE_INVALIDATE_BITS)) != 0; in iris_emit_raw_pipe_control()

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