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Searched refs:NZCV (Results 1 - 25 of 28) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64CondBrTuning.cpp10 /// into a conditional branch (B.cond), when the NZCV flags can be set for
89 // just make sure the implicit-def of NZCV isn't marked dead. in convertToFlagSetting()
94 if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV) in convertToFlagSetting()
144 // We don't want NZCV bits live across blocks. in tryToTuneBranch()
196 // reads NZCV. in tryToTuneBranch()
199 if (I->modifiesRegister(AArch64::NZCV, TRI) || in tryToTuneBranch()
200 I->readsRegister(AArch64::NZCV, TRI)) in tryToTuneBranch()
255 // reads NZCV. in tryToTuneBranch()
258 if (I->modifiesRegister(AArch64::NZCV, TRI) || in tryToTuneBranch()
259 I->readsRegister(AArch64::NZCV, TR in tryToTuneBranch()
[all...]
H A DAArch64ConditionalCompares.cpp64 STATISTIC(NumMultNZCVUses, "Number of ccmps rejected (NZCV used)");
65 STATISTIC(NumUnknNZCVDefs, "Number of ccmps rejected (NZCV def unknown)");
100 // operand that specifies the NZCV flag values when the condition is false and
304 if (!I->readsRegister(AArch64::NZCV)) { in findConvertibleCompare()
355 PhysRegInfo PRI = AnalyzePhysRegInBundle(*I, AArch64::NZCV, TRI); in findConvertibleCompare()
384 // Reject any live-in physregs. It's probably NZCV/EFLAGS, and very hard to in canSpeculateInstrs()
427 if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) { in canSpeculateInstrs()
685 // The NZCV immediate operand should provide flags for the case where Head in convert()
688 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(CmpBBTailCC); in convert() local
701 MIB.addImm(NZCV) in convert()
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H A DAArch64ConditionOptimizer.cpp155 // Since we may modify cmp of this MBB, make sure NZCV does not live out. in findSuitableCompare()
157 if (SuccBB->isLiveIn(AArch64::NZCV)) in findSuitableCompare()
164 // Check if there is any use of NZCV between CMP and Bcc. in findSuitableCompare()
165 if (I->readsRegister(AArch64::NZCV)) in findSuitableCompare()
H A DAArch64InstrInfo.cpp444 // if NZCV is used, do not fold. in canFoldIntoCSel()
445 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
472 // if NZCV is used, do not fold. in canFoldIntoCSel()
473 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
1011 // Replace SUBSWrr with SUBWrr if NZCV is not used.
1164 Instr.modifiesRegister(AArch64::NZCV, TRI)) || in areCFlagsAccessedBetweenInstrs()
1165 ((AccessToCheck & AK_Read) && Instr.readsRegister(AArch64::NZCV, TRI))) in areCFlagsAccessedBetweenInstrs()
1172 /// instruction which produces AArch64::NZCV. It can be truly compare
1188 // Replace SUBSWrr with SUBWrr if NZCV is not used. in optimizeCompareInstr()
1189 int DeadNZCVIdx = CmpInstr.findRegisterDefOperandIdx(AArch64::NZCV, tru in optimizeCompareInstr()
[all...]
H A DAArch64RedundantCopyElimination.cpp116 /// in \p MBB for some cases. Otherwise, we find and inspect the NZCV setting
119 /// \p MMB for some cases. In addition, if the NZCV setting instruction is
166 // Find compare instruction that sets NZCV used by CondBr. in knownRegValInBlock()
196 // We've found the instruction that sets NZCV. in knownRegValInBlock()
212 // The destination register must not be modified between the NZCV setting in knownRegValInBlock()
222 // Look for NZCV setting instructions that define something other than in knownRegValInBlock()
256 // The destination register of the NZCV setting instruction must not be in knownRegValInBlock()
261 // We've found the instruction that sets NZCV whose DstReg == 0. in knownRegValInBlock()
268 // Bail if we see an instruction that defines NZCV that we don't handle. in knownRegValInBlock()
269 if (PredI.definesRegister(AArch64::NZCV)) in knownRegValInBlock()
[all...]
H A DAArch64SpeculationHardening.cpp236 SplitEdgeBB.addLiveIn(AArch64::NZCV); in insertTrackingCode()
H A DAArch64FrameLowering.cpp1082 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define | RegState::Dead) in emitPrologue()
1107 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define | RegState::Dead) in emitPrologue()
H A DAArch64ExpandPseudoInsts.cpp216 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill); in expandCMP_SWAP()
H A DAArch64ISelLowering.cpp334 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences. in AArch64TargetLowering()
1459 TrueBB->addLiveIn(AArch64::NZCV); in EmitF128CSEL()
1460 EndBB->addLiveIn(AArch64::NZCV); in EmitF128CSEL()
1639 /// without a real NZCV register, so we have to use less efficient combinations
1755 /// a comparison. They set the NZCV flags to a predefined value if their
1833 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(InvOutCC); in emitConditionalComparison() local
1834 SDValue NZCVOp = DAG.getConstant(NZCV, DL, MVT::i32); in emitConditionalComparison()
1909 /// and conditional compare operations. @returns an NZCV flags producing node
4642 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be in LowerDarwinGlobalTLSAddress()
6309 return std::make_pair(unsigned(AArch64::NZCV), in getRegForInlineAsmConstraint()
[all...]
/third_party/vixl/test/aarch64/
H A Dtest-assembler-fp-aarch64.cc1725 __ Mrs(x0, NZCV); in TEST()
1729 __ Mrs(x1, NZCV); in TEST()
1733 __ Mrs(x2, NZCV); in TEST()
1737 __ Mrs(x3, NZCV); in TEST()
1741 __ Mrs(x4, NZCV); in TEST()
1745 __ Mrs(x5, NZCV); in TEST()
1749 __ Mrs(x6, NZCV); in TEST()
1753 __ Mrs(x7, NZCV); in TEST()
1760 __ Mrs(x8, NZCV); in TEST()
1766 __ Mrs(x9, NZCV); in TEST()
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H A Dtest-assembler-sve-aarch64.cc1085 __ Mrs(x0, NZCV);
1087 __ Mrs(x1, NZCV);
1143 __ Mrs(x6, NZCV);
1153 __ Mrs(x7, NZCV);
1164 __ Mrs(x8, NZCV);
1167 __ Mrs(x9, NZCV);
1177 __ Mrs(x10, NZCV);
1180 __ Mrs(x11, NZCV);
1240 __ Mrs(x2, NZCV);
1242 __ Mrs(x3, NZCV);
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H A Dtest-assembler-aarch64.cc2160 // Initialize NZCV with `eq` flags. in AdrpPageBoundaryHelper()
2240 // Initialize NZCV with `eq` flags.
5222 __ Msr(NZCV, x10);
5840 // Set NZCV to 0b1011 (0xb)
5842 __ Mrs(x1, NZCV);
5844 // Set NZCV to 0b0111 (0x7)
5846 __ Mrs(x2, NZCV);
5848 // Set Z to 0, NZCV = 0b0011 (0x3)
5850 __ Mrs(x3, NZCV);
5852 // Set N to 1 and C to 0, NZCV
[all...]
H A Dtest-utils-aarch64.cc700 __ Mrs(tmp, NZCV); in Dump()
891 __ Cmn(x0, 0); // Clear NZCV flags for later. in SetInitialMachineState()
964 __ Mrs(t1, NZCV); in ComputeMachineStateHash()
H A Dtest-disasm-aarch64.cc2567 COMPARE(ccmn(w0, w1, NZCVFlag, eq), "ccmn w0, w1, #NZCV, eq"); in TEST()
2609 COMPARE(mrs(x0, NZCV), "mrs x0, nzcv"); in TEST()
2610 COMPARE(mrs(x30, NZCV), "mrs x30, nzcv"); in TEST()
2626 COMPARE(msr(NZCV, x0), "msr nzcv, x0"); in TEST()
2627 COMPARE(msr(NZCV, x30), "msr nzcv, x30"); in TEST()
H A Dtest-simulator-aarch64.cc747 __ Mrs(flags, NZCV); in TestCmp_Helper()
793 // Each NZCV result only requires 4 bits. in TestCmp()
882 __ Mrs(flags, NZCV); in TestCmpZero_Helper()
924 // Each NZCV result only requires 4 bits. in TestCmpZero()
/third_party/vixl/tools/test_generator/
H A Ddata_types.py408 class NZCV(U32): class
410 Description of NZCV flags as inputs to an instruction.
413 and record the NZCV flags before and after emitting the instruction under
418 # When setting the `NZCV` flags, we need to make sure we do not override the
428 // Set the `NZCV` and `Q` flags together.
441 // Only record the NZCV bits.
458 # When clearing or setting the `Q` bit, we need to make sure the `NZCV`
465 // Save the `NZCV` flags.
468 // Set the `NZCV` and `Q` flags together.
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-arm64.cc114 case NZCV: in DefaultValueFor()
377 nzcv_ = SimSystemRegister::DefaultValueFor(NZCV); in ResetState()
1071 LogSystemRegister(NZCV); in AddWithCarry()
1192 LogSystemRegister(NZCV);
1368 PrintSystemRegister(NZCV);
1592 case NZCV:
1919 LogSystemRegister(NZCV);
1960 LogSystemRegister(NZCV);
3081 LogSystemRegister(NZCV);
3090 LogSystemRegister(NZCV);
[all...]
/third_party/vixl/benchmarks/aarch64/
H A Dbench-utils.cc204 __ Mrs(PickX(), NZCV); in GenerateTrivialSequence() local
/third_party/vixl/src/aarch64/
H A Dsimulator-aarch64.cc61 case NZCV: in DefaultValueFor()
574 nzcv_ = SimSystemRegister::DefaultValueFor(NZCV); in Simulator()
924 LogSystemRegister(NZCV); in Simulator()
944 // NZCV bits, ordered N in bit 3 to V in bit 0. in Simulator()
969 int carry_in = (sum_lo.second & 0x2) >> 1; // C flag in NZCV result. in Simulator()
1128 LogSystemRegister(NZCV); in Simulator()
1329 PrintSystemRegister(NZCV); in Simulator()
1715 case NZCV: in Simulator()
4061 LogSystemRegister(NZCV); in Simulator()
4100 LogSystemRegister(NZCV); in Simulator()
[all...]
H A Dmacro-assembler-aarch64.cc2650 // preserved, but NZCV and the caller-saved registers may be clobbered. in Emit()
2834 // Preserve all caller-saved registers as well as NZCV. in Emit()
2868 // Preserve NZCV. in Emit()
2870 Mrs(tmp, NZCV); in Emit()
2876 // Restore NZCV. in Emit()
2879 Msr(NZCV, tmp); in Emit()
H A Dconstants-aarch64.h227 /* NZCV */ \
233 M_(NZCV, Flags_mask) \
500 NZCV = SystemRegisterEncoder<3, 3, 4, 2, 0>::value, enumerator
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp130 {codeview::RegisterId::ARM64_NZCV, AArch64::NZCV}, in initLLVMToCVRegMapping()
/third_party/node/deps/v8/src/codegen/arm64/
H A Dconstants-arm64.h271 /* NZCV */ \
277 M_(NZCV, Flags_mask) \
438 NZCV = ((0x1 << SysO0_offset) | (0x3 << SysOp1_offset) | (0x4 << CRn_offset) | enumerator
H A Dmacro-assembler-arm64.cc3614 // Preserve all caller-saved registers as well as NZCV. in TruncateDoubleToI()
3650 // Preserve NZCV. in TruncateDoubleToI()
3654 Mrs(tmp, NZCV); in TruncateDoubleToI()
3660 // Restore NZCV. in TruncateDoubleToI()
3665 Msr(NZCV, tmp); in TruncateDoubleToI()
/third_party/node/deps/v8/src/diagnostics/arm64/
H A Ddisasm-arm64.cc1460 case NZCV: in VisitSystem()
1475 case NZCV: in VisitSystem()

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