| /third_party/vixl/test/aarch64/ |
| H A D | test-utils-aarch64.cc | 915 __ Mla(z0.VnD(), p0.Merging(), z30.VnD(), z0.VnD(), z31.VnD()); in SetInitialMachineState()
917 __ Mla(ZRegister(i).VnD(), in SetInitialMachineState()
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| H A D | test-disasm-sve-aarch64.cc | 2828 COMPARE_MACRO(Mla(z0.VnB(), p1.Merging(), z0.VnB(), z2.VnB(), z4.VnB()), in TEST()
2830 COMPARE_MACRO(Mla(z3.VnH(), p2.Merging(), z4.VnH(), z3.VnH(), z5.VnH()), in TEST()
2832 COMPARE_MACRO(Mla(z4.VnS(), p3.Merging(), z5.VnS(), z6.VnS(), z4.VnS()), in TEST()
2834 COMPARE_MACRO(Mla(z5.VnD(), p4.Merging(), z6.VnD(), z7.VnD(), z8.VnD()), in TEST()
8021 COMPARE_MACRO(Mla(z1.VnH(), z1.VnH(), z9.VnH(), z0.VnH(), 0), in TEST()
8023 COMPARE_MACRO(Mla(z1.VnH(), z1.VnH(), z9.VnH(), z1.VnH(), 2), in TEST()
8025 COMPARE_MACRO(Mla(z1.VnH(), z1.VnH(), z9.VnH(), z2.VnH(), 6), in TEST()
8027 COMPARE_MACRO(Mla(z1.VnH(), z1.VnH(), z9.VnH(), z3.VnH(), 7), in TEST()
8029 COMPARE_MACRO(Mla(z10.VnS(), z10.VnS(), z22.VnS(), z7.VnS(), 0), in TEST()
8031 COMPARE_MACRO(Mla(z1 in TEST()
[all...] |
| H A D | test-disasm-neon-aarch64.cc | 1700 COMPARE_MACRO(Mla(v19.M, v20.M, v21.M), "mla v19." S ", v20." S ", v21." S); in TEST()
2257 COMPARE_MACRO(Mla(v0.V4H(), v1.V4H(), v2.H(), 0), in TEST()
2259 COMPARE_MACRO(Mla(v2.V8H(), v3.V8H(), v15.H(), 7), in TEST()
2261 COMPARE_MACRO(Mla(v0.V2S(), v1.V2S(), v2.S(), 0), in TEST()
2263 COMPARE_MACRO(Mla(v2.V4S(), v3.V4S(), v15.S(), 3), in TEST()
2265 COMPARE_MACRO(Mla(v11.V2S(), v17.V2S(), v26.S(), 1), in TEST()
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| H A D | test-assembler-neon-aarch64.cc | 4381 __ Mla(v16.V16B(), v0.V16B(), v1.V16B()); in TEST()
4439 __ Mla(v20.V4H(), v0.V4H(), v1.H(), 0); in TEST()
4440 __ Mla(v21.V8H(), v0.V8H(), v1.H(), 7); in TEST()
4444 __ Mla(v22.V2S(), v0.V2S(), v1.S(), 0); in TEST()
4445 __ Mla(v23.V4S(), v0.V4S(), v1.S(), 3); in TEST()
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| H A D | test-assembler-sve-aarch64.cc | 400 // The Mla macro automatically selects between mla, mad and movprfx + mla
408 __ Mla(mla_da_result, p0.Merging(), mla_da_result, zn, zm);
411 __ Mla(mla_dn_result, p1.Merging(), za, mla_dn_result, zm);
414 __ Mla(mla_dm_result, p2.Merging(), za, zn, mla_dm_result);
417 __ Mla(mla_d_result, p3.Merging(), za, zn, zm);
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64.h | 220 V(mla, Mla) \
388 V(mla, Mla) \
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| H A D | IceInstARM32.h | 400 Mla, enumerator
1063 using InstARM32Mla = InstARM32FourAddrGPR<InstARM32::Mla>;
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| H A D | IceInstARM32.cpp | 3456 template class InstARM32FourAddrGPR<InstARM32::Mla>;
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-sve-aarch64.cc | 966 void MacroAssembler::Mla(const ZRegister& zd, in Mla() function in vixl::aarch64::MacroAssembler
1862 V(Mla, mla, FourRegOneImmDestructiveHelper) \
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| H A D | macro-assembler-aarch64.h | 2886 V(mla, Mla) \
3115 V(mla, Mla) \
5523 void Mla(const ZRegister& zd,
6778 void Mla(const ZRegister& zd,
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| /third_party/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.h | 2793 void Mla(Condition cond, Register rd, Register rn, Register rm, Register ra) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
2808 void Mla(Register rd, Register rn, Register rm, Register ra) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
2809 Mla(al, rd, rn, rm, ra); in MacroAssembler()
2811 void Mla(FlagsUpdate flags, in MacroAssembler() function in vixl::aarch32::MacroAssembler
2819 Mla(cond, rd, rn, rm, ra); in MacroAssembler()
2825 Mla(cond, rd, rn, rm, ra); in MacroAssembler()
2829 void Mla( in MacroAssembler() function in vixl::aarch32::MacroAssembler
2831 Mla(flags, al, rd, rn, rm, ra); in MacroAssembler()
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| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| H A D | code-generator-arm64.cc | 2177 SIMD_DESTRUCTIVE_BINOP_LANE_SIZE_CASE(kArm64Mla, Mla); in AssembleArchInstruction()
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