| /third_party/node/deps/v8/src/regexp/arm64/ |
| H A D | regexp-macro-assembler-arm64.cc | 322 __ Lsr(x11, GetCachedRegister(start_reg), kWRegSizeInBits); in CheckNotBackReferenceIgnoreCase()
475 __ Lsr(x11, GetCachedRegister(start_reg), kWRegSizeInBits); in CheckNotBackReference()
980 __ Lsr(capture_end.X(), capture_start.X(), kWRegSizeInBits); in GetCode()
1285 __ Lsr(current_input_offset().X(), GetCachedRegister(reg), in ReadCurrentPositionFromRegister()
1604 __ Lsr(maybe_result.X(), GetCachedRegister(register_index), in GetRegister()
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| /third_party/vixl/test/aarch32/ |
| H A D | test-disasm-a32.cc | 3472 COMPARE_T32(Lsr(eq, r0, r1, 16), in TEST()
3476 COMPARE_T32(Lsr(eq, r0, r1, 32), in TEST()
3480 COMPARE_T32(Lsr(eq, r0, r1, 0), in TEST()
3486 COMPARE_T32(Lsr(eq, r7, r7, r3), in TEST()
3490 COMPARE_T32(Lsr(eq, r8, r8, r3), in TEST()
4072 CHECK_T32_16(Lsr(DontCare, r0, r1, 32), "lsrs r0, r1, #32\n"); in TEST()
4074 CHECK_T32_16_IT_BLOCK(Lsr(DontCare, eq, r0, r1, 32), in TEST()
4078 CHECK_T32_16(Lsr(DontCare, r0, r0, r1), "lsrs r0, r1\n"); in TEST()
4080 CHECK_T32_16_IT_BLOCK(Lsr(DontCare, eq, r0, r0, r1), in TEST()
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| H A D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 146 M(Lsr) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 146 M(Lsr) \
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| H A D | test-assembler-aarch32.cc | 784 __ Lsr(r4, r1, 8); in TEST()
810 __ Lsr(r4, r1, r9); in TEST()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64-inl.h | 787 void TurboAssembler::Lsr(const Register& rd, const Register& rn, in Lsr() function in v8::internal::TurboAssembler
794 void TurboAssembler::Lsr(const Register& rd, const Register& rn, in Lsr() function in v8::internal::TurboAssembler
1103 Lsr(smi, smi, kSmiShift); in SmiToInt32()
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| H A D | macro-assembler-arm64.h | 1060 inline void Lsr(const Register& rd, const Register& rn, unsigned shift);
1061 inline void Lsr(const Register& rd, const Register& rn, const Register& rm);
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| /third_party/vixl/test/aarch64/ |
| H A D | test-assembler-sve-aarch64.cc | 8532 __ Lsr(x1, x1, 1);
8541 __ Lsr(x2, x2, 2);
9526 __ Lsr(z29.VnD(), z28.VnD(), 1); // Shift right to 0x4000000040000000
9531 __ Lsr(z29.VnD(), z29.VnD(), 1); // Shift right to 0x2000000020000000
9536 __ Lsr(z29.VnD(), z29.VnD(), 1); // Shift right to 0x1000000010000000
9720 __ Lsr(z29.VnD(), z28.VnD(), 1); // Shift right to 0x4000000040000000
9725 __ Lsr(z29.VnD(), z29.VnD(), 1); // Shift right to 0x2000000020000000
9730 __ Lsr(z29.VnD(), z29.VnD(), 1); // Shift right to 0x1000000010000000
9897 __ Lsr(zn, zn, shift);
10422 __ Lsr(x
[all...] |
| H A D | test-utils-aarch64.cc | 975 __ Lsr(t2, t2, 4); in ComputeMachineStateHash()
|
| H A D | test-assembler-aarch64.cc | 6621 __ Lsr(x16, x0, x1);
6622 __ Lsr(x17, x0, x2);
6623 __ Lsr(x18, x0, x3);
6624 __ Lsr(x19, x0, x4);
6625 __ Lsr(x20, x0, x5);
6626 __ Lsr(x21, x0, x6);
6628 __ Lsr(w22, w0, w1);
6629 __ Lsr(w23, w0, w2);
6630 __ Lsr(w24, w0, w3);
6631 __ Lsr(w2
[all...] |
| H A D | test-disasm-sve-aarch64.cc | 360 COMPARE_MACRO(Lsr(z4.VnB(), p0.Merging(), z4.VnB(), z30.VnB()), in TEST()
362 COMPARE_MACRO(Lsr(z4.VnB(), p0.Merging(), z30.VnB(), z4.VnB()), in TEST()
364 COMPARE_MACRO(Lsr(z4.VnB(), p0.Merging(), z10.VnB(), z14.VnB()), in TEST()
406 COMPARE_MACRO(Lsr(z24.VnD(), p2.Merging(), z0.VnD(), 64), in TEST()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/DartARM32/ |
| H A D | assembler_arm.h | 998 void Lsr(Register rd, Register rm, const Operand& shift_imm,
1001 void Lsr(Register rd, Register rm, Register rs, Condition cond = AL);
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| H A D | assembler_arm.cc | 2458 void Assembler::Lsr(Register rd, Register rm, const Operand& shift_imm,
2462 ASSERT(shift != 0); // Do not use Lsr if no shift is wanted.
2470 void Assembler::Lsr(Register rd, Register rm, Register rs, Condition cond) {
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| /third_party/node/deps/v8/src/builtins/arm64/ |
| H A D | builtins-arm64.cc | 1042 __ Lsr(params_size, params_size, kSystemPointerSizeLog2); in LeaveInterpreterFrame()
1512 __ Lsr(x11, x11, kSystemPointerSizeLog2); in Generate_InterpreterEntryTrampoline()
3975 __ Lsr(unwind_limit, unwind_limit, kSystemPointerSizeLog2); in Generate_DeoptimizationEntry()
4012 __ Lsr(frame_size, x3, kSystemPointerSizeLog2); in Generate_DeoptimizationEntry()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| H A D | IceInstARM32.h | 398 Lsr, enumerator
1009 using InstARM32Lsr = InstARM32ThreeAddrGPR<InstARM32::Lsr>;
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| H A D | IceInstARM32.cpp | 3412 template class InstARM32ThreeAddrGPR<InstARM32::Lsr>;
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.h | 2159 void Lsr(const Register& rd, const Register& rn, unsigned shift) { in Lsr() function in vixl::aarch64::MacroAssembler
2166 void Lsr(const Register& rd, const Register& rn, const Register& rm) { in Lsr() function in vixl::aarch64::MacroAssembler
5423 void Lsr(const ZRegister& zd, in Lsr() function in vixl::aarch64::MacroAssembler
5431 void Lsr(const ZRegister& zd,
5435 void Lsr(const ZRegister& zd, const ZRegister& zn, int shift) { in Lsr() function in vixl::aarch64::MacroAssembler
5440 void Lsr(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in Lsr() function in vixl::aarch64::MacroAssembler
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| H A D | macro-assembler-sve-aarch64.cc | 671 V(Lsr, lsr) \
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| /third_party/node/deps/v8/src/wasm/baseline/arm64/ |
| H A D | liftoff-assembler-arm64.h | 1111 I32_SHIFTOP(i32_shr, Lsr)
1120 I64_SHIFTOP(i64_shr, Lsr)
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| /third_party/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.h | 2718 void Lsr(Condition cond, Register rd, Register rm, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
2739 void Lsr(Register rd, Register rm, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
2740 Lsr(al, rd, rm, operand); in MacroAssembler()
2742 void Lsr(FlagsUpdate flags, in MacroAssembler() function in vixl::aarch32::MacroAssembler
2749 Lsr(cond, rd, rm, operand); in MacroAssembler()
2763 Lsr(cond, rd, rm, operand); in MacroAssembler()
2768 void Lsr(FlagsUpdate flags, in MacroAssembler() function in vixl::aarch32::MacroAssembler
2772 Lsr(flags, al, rd, rm, operand); in MacroAssembler()
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| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| H A D | code-generator-arm64.cc | 1425 ASSEMBLE_SHIFT(Lsr, 64); in AssembleArchInstruction()
1428 ASSEMBLE_SHIFT(Lsr, 32); in AssembleArchInstruction()
|