| /third_party/vixl/examples/aarch64/ |
| H A D | neon-matrix-multiply.cc | 39 // __ Fmla(v<v_out>.V4S(), v5.V4S(), v<s_column>.S(), 1);
40 // __ Fmla(v<v_out>.V4S(), v6.V4S(), v<s_column>.S(), 2);
41 // __ Fmla(v<v_out>.V4S(), v7.V4S(), v<s_column>.S(), 3);
55 __ Fmla(v_out, v5.V4S(), v_in, 1); in GenerateMultiplyColumn()
56 __ Fmla(v_out, v6.V4S(), v_in, 2); in GenerateMultiplyColumn()
57 __ Fmla(v_out, v7.V4S(), v_in, 3); in GenerateMultiplyColumn()
|
| /third_party/vixl/test/aarch64/ |
| H A D | test-disasm-neon-aarch64.cc | 1805 COMPARE_MACRO(Fmla(v6.V8H(), v7.V8H(), v8.V8H()), "fmla v6.8h, v7.8h, v8.8h"); in TEST()
1806 COMPARE_MACRO(Fmla(v9.V4H(), v10.V4H(), v11.V4H()), in TEST()
2012 COMPARE_MACRO(Fmla(v1.M, v2.M, v3.M), "fmla v1." S ", v2." S ", v3." S); in TEST()
2518 COMPARE_MACRO(Fmla(v0.V4H(), v1.V4H(), v2.H(), 0), in TEST()
2520 COMPARE_MACRO(Fmla(v2.V8H(), v3.V8H(), v15.H(), 7), in TEST()
2522 COMPARE_MACRO(Fmla(v0.V2S(), v1.V2S(), v2.S(), 0), in TEST()
2524 COMPARE_MACRO(Fmla(v2.V4S(), v3.V4S(), v15.S(), 3), in TEST()
2526 COMPARE_MACRO(Fmla(v2.V4S(), v3.V4S(), v31.S(), 3), in TEST()
2528 COMPARE_MACRO(Fmla(v0.V2D(), v1.V2D(), v2.D(), 0), in TEST()
2530 COMPARE_MACRO(Fmla(v in TEST()
[all...] |
| H A D | test-utils-aarch64.cc | 839 __ Fmla(z0.WithLaneSize(esize), in SetFpData()
847 __ Fmla(ZRegister(i).WithLaneSize(esize), in SetFpData()
|
| H A D | test-disasm-sve-aarch64.cc | 1626 COMPARE_MACRO(Fmla(z0.VnH(), p1.Merging(), z0.VnH(), z2.VnH(), z4.VnH()), in TEST()
1628 COMPARE_MACRO(Fmla(z3.VnH(), p2.Merging(), z4.VnH(), z3.VnH(), z5.VnH()), in TEST()
1630 COMPARE_MACRO(Fmla(z4.VnS(), p3.Merging(), z5.VnS(), z6.VnS(), z4.VnS()), in TEST()
1634 COMPARE_MACRO(Fmla(z5.VnD(), p4.Merging(), z6.VnD(), z7.VnD(), z8.VnD()), in TEST()
1689 COMPARE_MACRO(Fmla(z0.VnH(), p1.Merging(), z0.VnH(), z2.VnH(), z4.VnH()), in TEST()
1691 COMPARE_MACRO(Fmla(z3.VnH(), p2.Merging(), z4.VnH(), z3.VnH(), z5.VnH()), in TEST()
1693 COMPARE_MACRO(Fmla(z4.VnS(), p3.Merging(), z5.VnS(), z6.VnS(), z4.VnS()), in TEST()
1695 COMPARE_MACRO(Fmla(z5.VnD(), p4.Merging(), z6.VnD(), z7.VnD(), z8.VnD()), in TEST()
1771 COMPARE_MACRO(Fmla(z10.VnH(), z11.VnH(), z12.VnH(), z4.VnH(), 7), in TEST()
1774 COMPARE_MACRO(Fmla(z1 in TEST()
[all...] |
| H A D | test-assembler-neon-aarch64.cc | 9308 __ Fmla(v16.V2S(), v1.V2S(), v2.V2S()); in TEST()
9309 __ Fmla(v17.V4S(), v1.V4S(), v2.V4S()); in TEST()
9310 __ Fmla(v18.V2D(), v1.V2D(), v2.V2D()); in TEST()
9351 __ Fmla(v16.V8H(), v0.V8H(), v1.V8H()); in TEST()
9352 __ Fmla(v17.V8H(), v2.V8H(), v3.V8H()); in TEST()
9353 __ Fmla(v18.V8H(), v2.V8H(), v6.V8H()); in TEST()
9354 __ Fmla(v19.V8H(), v3.V8H(), v6.V8H()); in TEST()
9355 __ Fmla(v20.V4H(), v0.V4H(), v1.V4H()); in TEST()
9356 __ Fmla(v21.V4H(), v2.V4H(), v3.V4H()); in TEST()
9357 __ Fmla(v2 in TEST()
[all...] |
| H A D | test-assembler-sve-aarch64.cc | 16680 // Fmla macro automatically selects between fmla, fmad and movprfx + fmla
16743 &MacroAssembler::Fmla,
16757 &MacroAssembler::Fmla,
16771 &MacroAssembler::Fmla,
16991 // Indexed form of Fmla and Fmls won't swap argument, passing strict NaN
17060 // Using the vector form of Fmla and Fmls to verify the indexed form.
17062 &MacroAssembler::Fmla, // vector form
17063 &MacroAssembler::Fmla, // indexed form
17082 &MacroAssembler::Fmla, // vector form
17083 &MacroAssembler::Fmla, // indexe
[all...] |
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64.h | 215 V(fmla, Fmla) \
382 V(fmla, Fmla) \
|
| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-sve-aarch64.cc | 1856 V(Fmla, fmla, FourRegOneImmDestructiveHelper) \
2019 void MacroAssembler::Fmla(const ZRegister& zd, in Fmla() function in vixl::aarch64::MacroAssembler
|
| H A D | macro-assembler-aarch64.h | 2877 V(fmla, Fmla) \
3107 V(fmla, Fmla) \
4640 void Fmla(
4647 void Fmla(const ZRegister& zd,
|
| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| H A D | code-generator-arm64.cc | 2276 SIMD_DESTRUCTIVE_BINOP_CASE(kArm64F64x2Qfma, Fmla, 2D); in AssembleArchInstruction()
2312 SIMD_DESTRUCTIVE_BINOP_CASE(kArm64F32x4Qfma, Fmla, 4S); in AssembleArchInstruction()
|