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Searched refs:DCB_DSCSR_SBRSELEN_Pos (Results 1 - 6 of 6) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_cm23.h1115 #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ macro
1116 #define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
H A Dcore_cm35p.h1926 #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ macro
1927 #define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
H A Dcore_cm33.h1926 #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ macro
1927 #define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
H A Dcore_starmc1.h2020 #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ macro
2021 #define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
H A Dcore_cm85.h3442 #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ macro
3443 #define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
H A Dcore_cm55.h3418 #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ macro
3419 #define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */

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