| /third_party/typescript/tests/baselines/reference/ |
| H A D | undefinedIsSubtypeOfEverything.js | 114 class D16 extends Base {
305 var D16 = /** @class */ (function (_super) {
306 __extends(D16, _super);
307 function D16() {
310 return D16;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIAddIMGInit.cpp | 81 MachineOperand *D16 = TII->getNamedOperand(MI, AMDGPU::OpName::d16); in runOnMachineFunction() local
89 unsigned D16Val = D16 ? D16->getImm() : 0; in runOnMachineFunction()
115 // When D16 then we want next whole VGPR after write data. in runOnMachineFunction()
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| H A D | SIInstrInfo.cpp | 3410 const MachineOperand *D16 = getNamedOperand(MI, AMDGPU::OpName::d16);
3413 if (D16 && D16->getImm() && !ST.hasUnpackedD16VMem())
6370 // Adjust the encoding family to GFX80 for D16 buffer instructions when the
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Support/ |
| H A D | ARMTargetParser.cpp | 177 {"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::D16}, in getFPUFeatures()
180 {"+vfp3d16", "-vfp3d16", FPUVersion::VFPV3, FPURestriction::D16}, in getFPUFeatures()
185 {"+vfp4d16", "-vfp4d16", FPUVersion::VFPV4, FPURestriction::D16}, in getFPUFeatures()
189 {"+fp-armv8d16", "-fp-armv8d16", FPUVersion::VFPV5, FPURestriction::D16}, in getFPUFeatures()
193 {"+fp64", "-fp64", FPUVersion::VFPV2, FPURestriction::D16}, in getFPUFeatures()
467 // restriction), D16 (only 16 d-regs) and SP_D16 (16 d-regs in findDoublePrecisionFPU()
469 // SP restriction without D16. So this test just means 'is it in findDoublePrecisionFPU()
475 // that SP_D16 has been replaced with just D16, representing adding in findDoublePrecisionFPU()
480 CandidateFPU.Restriction == ARM::FPURestriction::D16) { in findDoublePrecisionFPU()
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| /third_party/FreeBSD/lib/msun/ld128/ |
| H A D | s_expl.c | 191 * With my coeffs (D11-D16 double):
198 D16 = 4.7628892832607741e-14, /* 0x1.ad00Dfe41feccp-45 */ variable
257 dx * (D14 + dx * (D15 + dx * (D16 + in expm1l()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 82 case D19: case D18: case D17: case D16: in isARMArea3Register()
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| H A D | ARMBaseRegisterInfo.cpp | 204 // Reserve D16-D31 if the subtarget doesn't support them. in getReservedRegs()
206 static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!"); in getReservedRegs()
208 markSuperRegs(Reserved, ARM::D16 + R); in getReservedRegs()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/ |
| H A D | ARMTargetParser.h | 137 D16, ///< Only 16 D registers member in llvm::ARM::FPURestriction
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 127 case AArch64::D16: return AArch64::B16; in getBRegFromDReg()
167 case AArch64::B16: return AArch64::D16; in getDRegFromBReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| H A D | SparcRegisterInfo.cpp | 92 for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI) in getReservedRegs()
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| /third_party/skia/third_party/externals/angle2/src/image_util/ |
| H A D | imageformats.h | 773 struct D16 struct
777 static void ReadDepthStencil(DepthStencil *dst, const D16 *src);
778 static void WriteDepthStencil(D16 *dst, const DepthStencil *src);
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| H A D | imageformats.cpp | 1901 void D16::ReadDepthStencil(DepthStencil *dst, const D16 *src) in ReadDepthStencil()
1907 void D16::WriteDepthStencil(D16 *dst, const DepthStencil *src) in WriteDepthStencil()
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| /third_party/backends/backend/ |
| H A D | snapscan.c | 352 given D(n/2) and n; n is presumed to be a power of 2. D8 and D16
358 static u_char D4[16], D8[64], D16[256]; variable
774 mkDn (D16, D8, 16); in sane_init()
1555 matrix = D16; in download_halftone_matrices()
1556 matrix_sz = sizeof (D16); in download_halftone_matrices()
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| /third_party/mesa3d/src/broadcom/vulkan/ |
| H A D | v3dvx_formats.c | 141 FORMAT(D16_UNORM, D16, DEPTH_COMP16, SWIZ_X001, 32, false),
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| /third_party/mesa3d/src/gallium/drivers/v3d/ |
| H A D | v3dx_format_table.c | 153 FORMAT(Z16_UNORM, D16, DEPTH_COMP16,SWIZ_XXXX, 32, 1),
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| /third_party/mesa3d/src/gallium/drivers/etnaviv/ |
| H A D | etnaviv_format.c | 112 _T(Z16_UNORM, D16, NONE),
302 /* apparently D16 can't use int filter but D24 can */ in texture_use_int_filter()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 120 case AArch64::D16: in isOdd()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 521 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); in convertMIMGInst() local
522 if (D16 && AMDGPU::hasPackedD16(STI)) { in convertMIMGInst()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 179 {codeview::RegisterId::ARM64_D16, AArch64::D16}, in initLLVMToCVRegMapping()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 81 SP::D0, SP::D16, SP::D1, SP::D17,
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| /third_party/skia/third_party/externals/angle2/src/libANGLE/renderer/ |
| H A D | Format_table_autogen.cpp | 28 { FormatID::D16_UNORM, GL_DEPTH_COMPONENT16, GL_DEPTH_COMPONENT16, nullptr, NoCopyFunctions, ReadDepthStencil<D16>, WriteDepthStencil<D16>, GL_UNSIGNED_NORMALIZED, 0, 0, 0, 0, 0, 16, 0, 2, std::numeric_limits<GLuint>::max(), false, false, false, false, false, gl::VertexAttribType::InvalidEnum },
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 153 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 337 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1320 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 3934 // Some FPUs only have 16 D registers, so D16-D31 are invalid in tryParseRegister()
3935 if (!hasD32() && RegNum >= ARM::D16 && RegNum <= ARM::D31) in tryParseRegister()
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