| /third_party/typescript/tests/baselines/reference/ |
| H A D | undefinedIsSubtypeOfEverything.js | 73 class D10 extends Base {
244 var D10 = /** @class */ (function (_super) {
245 __extends(D10, _super);
246 function D10() {
249 return D10;
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| /third_party/FreeBSD/lib/msun/ld128/ |
| H A D | s_expl.c | 183 D10 = 2.75573192239853161148064676533754048e-7L, variable
255 x * (D7 + x * (D8 + x * (D9 + x * (D10 + in expm1l()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 76 case D11: case D10: case D9: case D8: in isARMArea3Register()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.h | 89 { Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 },
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| H A D | HexagonFrameLowering.cpp | 931 Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13, in insertCFIInstructionsAt()
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| H A D | HexagonISelLowering.cpp | 285 .Case("r21:20", Hexagon::D10) in getRegisterByName()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 121 case AArch64::D10: return AArch64::B10; in getBRegFromDReg()
161 case AArch64::B10: return AArch64::D10; in getDRegFromBReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 117 case AArch64::D10: in isOdd()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 587 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, in DecodeDoubleRegsRegisterClass()
597 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; in DecodeGeneralDoubleLow8RegsRegisterClass()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AsmBackend.cpp | 673 // D10/D11 pair = 0x00000200,
679 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 &&
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| H A D | AArch64MCTargetDesc.cpp | 173 {codeview::RegisterId::ARM64_D10, AArch64::D10}, in initLLVMToCVRegMapping()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 86 SP::D10, SP::D26, SP::D11, SP::D27,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAsmBackend.cpp | 1254 static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 }; in generateCompactUnwindEncoding()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCDuplexInfo.cpp | 692 case Hexagon::D10: in addOps()
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| H A D | HexagonMCInstrInfo.cpp | 254 case D10: in getDuplexRegisterNumbering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 151 Sparc::D8, Sparc::D9, Sparc::D10, Sparc::D11,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 336 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1318 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3241 case Mips::D10: return Mips::F21; in nextReg()
|