| /third_party/vixl/test/aarch32/ |
| H A D | test-simulator-cond-rd-operand-const-a32.cc | 116 M(Cmn) \
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| H A D | test-simulator-cond-rd-operand-const-t32.cc | 116 M(Cmn) \
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| H A D | test-simulator-cond-rd-operand-rn-a32.cc | 116 M(Cmn) \
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| H A D | test-simulator-cond-rd-operand-rn-t32.cc | 116 M(Cmn) \
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| H A D | test-disasm-a32.cc | 2348 TEST_SHIFT_T32(Cmn, "cmn", 0x0000000a) in TEST()
2370 TEST_WIDE_IMMEDIATE(Cmn, "cmn", 0x0000000e); in TEST()
2373 TEST_WIDE_IMMEDIATE_PC(Cmn, "cmn", 0x0000000e); in TEST()
3318 COMPARE_T32(Cmn(eq, r0, r1), in TEST()
3322 COMPARE_T32(Cmn(eq, r0, r8), in TEST()
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| H A D | test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc | 116 M(Cmn) \
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| H A D | test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc | 116 M(Cmn) \
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| H A D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 116 M(Cmn) \
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| H A D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 116 M(Cmn) \
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| H A D | test-simulator-cond-rd-operand-rn-shift-rs-a32.cc | 116 M(Cmn) \
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| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| H A D | code-generator-arm64.cc | 1568 __ Cmn(i.InputOrZeroRegister64(0), i.InputOperand2_64(1)); in AssembleArchInstruction()
1571 __ Cmn(i.InputOrZeroRegister32(0), i.InputOperand2_32(1)); in AssembleArchInstruction()
1722 __ Cmn(i.OutputRegister32(), 1); in AssembleArchInstruction()
1737 __ Cmn(i.OutputRegister32(), 1); in AssembleArchInstruction()
1765 __ Cmn(i.OutputRegister64(), 1); in AssembleArchInstruction()
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| /third_party/node/deps/v8/src/regexp/arm64/ |
| H A D | regexp-macro-assembler-arm64.cc | 339 __ Cmn(capture_length, current_input_offset()); in CheckNotBackReferenceIgnoreCase()
492 __ Cmn(capture_length, current_input_offset()); in CheckNotBackReference()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| H A D | IceInstARM32.h | 388 Cmn, enumerator
1065 using InstARM32Cmn = InstARM32CmpLike<InstARM32::Cmn>;
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| H A D | IceInstARM32.cpp | 3459 template class InstARM32CmpLike<InstARM32::Cmn>;
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| /third_party/vixl/test/aarch64/ |
| H A D | test-utils-aarch64.cc | 891 __ Cmn(x0, 0); // Clear NZCV flags for later. in SetInitialMachineState()
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| H A D | test-disasm-aarch64.cc | 2845 COMPARE_MACRO(Cmn(w0, -1), "cmp w0, #0x1 (1)"); in TEST()
2846 COMPARE_MACRO(Cmn(x1, -1), "cmp x1, #0x1 (1)"); in TEST()
2847 COMPARE_MACRO(Cmn(w2, -4095), "cmp w2, #0xfff (4095)"); in TEST()
2848 COMPARE_MACRO(Cmn(x3, -4095), "cmp x3, #0xfff (4095)"); in TEST()
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| H A D | test-assembler-aarch64.cc | 6031 __ Cmn(x1, Operand(x0));
6043 __ Cmn(w1, Operand(w0));
6055 __ Cmn(x1, Operand(x0));
6067 __ Cmn(w1, Operand(w0));
7159 __ Cmn(w1, w1); // Set N and V.
7161 // The Msr should have overwritten every flag set by the Cmn.
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64-inl.h | 158 void TurboAssembler::Cmn(const Register& rn, const Operand& operand) { in Cmn() function in v8::internal::TurboAssembler
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| H A D | macro-assembler-arm64.h | 1064 inline void Cmn(const Register& rn, const Operand& operand);
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.cc | 1599 void MacroAssembler::Cmn(const Register& rn, const Operand& operand) { in Emit() function in vixl::aarch64::MacroAssembler
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| H A D | macro-assembler-aarch64.h | 816 void Cmn(const Register& rn, const Operand& operand);
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| /third_party/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.h | 1778 void Cmn(Condition cond, Register rn, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
1795 void Cmn(Register rn, const Operand& operand) { Cmn(al, rn, operand); } in MacroAssembler() function in vixl::aarch32::MacroAssembler
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