Home
last modified time | relevance | path

Searched refs:CACR (Results 1 - 2 of 2) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_cm7.h517 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ member
884 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
885 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
887 #define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */
888 #define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */
890 #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
891 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
H A Dcore_starmc1.h584 __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ member
993 #define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */
994 #define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */
996 #define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */
997 #define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */
999 #define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */
1000 #define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */
1002 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
1003 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */

Completed in 14 milliseconds