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Searched refs:BITFIELD64_MASK (Results 1 - 25 of 33) sorted by relevance

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/third_party/mesa3d/src/panfrost/bifrost/
H A Dbi_opt_dce.c87 live &= ~(BITFIELD64_MASK(nr) << reg); in bi_postra_liveness_ins()
95 live |= (BITFIELD64_MASK(nr) << reg); in bi_postra_liveness_ins()
170 uint64_t mask = (BITFIELD64_MASK(nr) << reg); in bi_opt_dce_post_ra()
H A Dbi_scoreboard.c124 mask |= (BITFIELD64_MASK(count) << reg); in bi_read_mask()
147 mask |= (BITFIELD64_MASK(count) << reg); in bi_write_mask()
162 mask |= (BITFIELD64_MASK(count) << reg); in bi_write_mask()
H A Dbi_ra.c243 clobbered |= BITFIELD64_MASK(32) << 16; in bi_make_affinity()
320 uint64_t clobber = BITFIELD64_MASK(16) | BITFIELD64_BIT(48); in bi_mark_interference()
366 ctx->inputs->is_blend ? BITFIELD64_MASK(16) : in bi_allocate_registers()
367 full_regs ? BITFIELD64_MASK(64) : in bi_allocate_registers()
368 (BITFIELD64_MASK(16) | (BITFIELD64_MASK(16) << 48)); in bi_allocate_registers()
372 default_affinity &= BITFIELD64_MASK(48) << 8; in bi_allocate_registers()
/third_party/mesa3d/src/util/
H A Dmacros.h383 #define BITFIELD64_MASK(b) \ macro
387 (BITFIELD64_MASK((b) + (count)) & ~BITFIELD64_MASK(b))
/third_party/mesa3d/src/panfrost/bifrost/valhall/
H A Dva_mark_last.c62 mask |= (BITFIELD64_MASK(count) << reg); in bi_staging_read_mask()
165 uint64_t mask = BITFIELD64_MASK(nr) << I->src[s].value; in va_mark_last()
H A Dva_insert_flow.c80 mask |= (BITFIELD64_MASK(count) << reg); in bi_read_mask()
100 mask |= (BITFIELD64_MASK(count) << reg); in bi_write_mask()
/third_party/mesa3d/src/intel/compiler/
H A Dbrw_vue_map.c188 uint64_t builtins = slots_valid & BITFIELD64_MASK(VARYING_SLOT_VAR0); in brw_compute_vue_map()
198 uint64_t generics = slots_valid & ~BITFIELD64_MASK(VARYING_SLOT_VAR0); in brw_compute_vue_map()
H A Dbrw_fs_combine_constants.cpp614 (uint64_t)(imm->d & BITFIELD64_MASK(imm->size * 8)), in opt_combine_constants()
H A Dbrw_ir_fs.h308 reg.u64 &= BITFIELD64_MASK(bit_size);
H A Dbrw_reg.h1023 reg.u64 &= BITFIELD64_MASK(bit_size);
H A Dbrw_nir.c284 BITFIELD64_MASK(attr)); in brw_nir_lower_vs_inputs()
/third_party/mesa3d/src/mesa/vbo/
H A Dvbo_attrib.h110 #define VBO_ATTRIBS_LEGACY (BITFIELD64_MASK(VBO_ATTRIB_GENERIC0) | \
/third_party/mesa3d/src/compiler/nir/
H A Dnir_builder.h639 y &= BITFIELD64_MASK(x->bit_size); in nir_iadd_imm()
688 y &= BITFIELD64_MASK(x->bit_size); in _nir_mul_imm()
732 y &= BITFIELD64_MASK(x->bit_size); in nir_iand_imm()
736 } else if (y == BITFIELD64_MASK(x->bit_size)) { in nir_iand_imm()
746 assert(mask <= BITFIELD64_MASK(x->bit_size)); in nir_test_mask()
754 y &= BITFIELD64_MASK(x->bit_size); in nir_ior_imm()
758 } else if (y == BITFIELD64_MASK(x->bit_size)) { in nir_ior_imm()
800 y &= BITFIELD64_MASK(x->bit_size); in nir_udiv_imm()
H A Dnir.c39 #include "main/menums.h" /* BITFIELD64_MASK */
2676 * new_loc = loc + util_bitcount(dual_slot & BITFIELD64_MASK(loc))
2687 *dual_slot |= BITFIELD64_MASK(slots) << var->data.location; in nir_remap_dual_slot_attributes()
2693 util_bitcount64(*dual_slot & BITFIELD64_MASK(var->data.location)); in nir_remap_dual_slot_attributes()
2706 uint64_t mask = BITFIELD64_MASK(loc + 1); in nir_get_single_slot_attribs_mask()
H A Dnir_opt_load_store_vectorize.c1060 uint64_t mask = BITFIELD64_MASK(bits); in addition_wraps()
1101 max_low = round_down(BITFIELD64_MASK(addition_bits), stride) + (low->offset % stride); in check_for_robustness()
/third_party/mesa3d/src/gallium/drivers/nouveau/
H A Dnouveau_screen.c271 } while ((start + screen->svm_cutout_size) < BITFIELD64_MASK(limit_bit)); in nouveau_screen_init()
/third_party/mesa3d/src/gallium/drivers/iris/
H A Diris_program.c850 assert(bt->used_mask[group] == BITFIELD64_MASK(bt->sizes[group])); in rewrite_src_with_bti()
868 bt->used_mask[group] = BITFIELD64_MASK(bt->sizes[group]); in mark_used_with_src()
903 BITFIELD64_MASK(num_render_targets); in iris_setup_binding_table()
911 BITFIELD64_MASK(num_render_targets); in iris_setup_binding_table()
1011 bt->used_mask[i] = BITFIELD64_MASK(bt->sizes[i]); in iris_setup_binding_table()
/third_party/mesa3d/src/gallium/frontends/lavapipe/
H A Dlvp_pipeline.c143 uint64_t mask = BITFIELD64_MASK(MAX2(size, 1)) << value; in set_image_access()
178 uint64_t mask = BITFIELD64_MASK(MAX2(size, 1)) << value; in set_buffer_access()
/third_party/mesa3d/src/gallium/drivers/crocus/
H A Dcrocus_program.c768 assert(bt->used_mask[group] == BITFIELD64_MASK(bt->sizes[group])); in rewrite_src_with_bti()
786 bt->used_mask[group] = BITFIELD64_MASK(bt->sizes[group]); in mark_used_with_src()
822 BITFIELD64_MASK(num_render_targets); in crocus_setup_binding_table()
830 BITFIELD64_MASK(num_render_targets); in crocus_setup_binding_table()
943 bt->used_mask[i] = BITFIELD64_MASK(bt->sizes[i]); in crocus_setup_binding_table()
/third_party/mesa3d/src/microsoft/spirv_to_dxil/
H A Ddxil_spirv_nir.c526 kill_var_mask &= BITFIELD64_MASK(MAX_VARYING) << VARYING_SLOT_VAR0; in dxil_spirv_nir_kill_unused_outputs()
/third_party/mesa3d/src/gallium/auxiliary/nir/
H A Dnir_to_tgsi_info.c768 BITFIELD64_MASK(location)); in nir_tgsi_scan_shader()
/third_party/mesa3d/src/mesa/state_tracker/
H A Dst_glsl_to_nir.cpp110 BITFIELD64_MASK(var->data.location)); in st_nir_assign_vs_in_locations()
/third_party/mesa3d/src/panfrost/vulkan/
H A Dpanvk_vX_pipeline.c858 BITFIELD64_MASK(attrib)); in panvk_pipeline_builder_parse_vertex_input()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_gfx_cs.c307 ctx->tracked_regs.reg_saved = BITFIELD64_MASK(SI_TRACKED_GE_PC_ALLOC); in si_set_tracked_regs_to_clear_state()
/third_party/mesa3d/src/amd/common/
H A Dac_nir_lower_ngg.c1736 unsigned packed_location = util_bitcount64((b->shader->info.outputs_written & BITFIELD64_MASK(slot))); in lower_ngg_gs_emit_vertex_with_counter()
1911 unsigned packed_location = util_bitcount64((b->shader->info.outputs_written & BITFIELD64_MASK(slot))); in ngg_gs_export_vertices()

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