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Searched refs:Adds (Results 1 - 25 of 28) sorted by relevance

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/third_party/vixl/test/aarch32/
H A Dtest-disasm-a32.cc633 COMPARE_T32(Adds(r0, r0, Operand(r0, ROR, r0)), in TEST()
1519 COMPARE_A32(Adds(r0, r1, -1), "subs r0, r1, #1\n"); in TEST()
1522 COMPARE_T32(Adds(r0, r1, -1), "adds r0, r1, #4294967295\n"); in TEST()
1525 COMPARE_BOTH(Adds(r0, r1, -4), "subs r0, r1, #4\n"); in TEST()
2661 COMPARE_A32(Adds(pc, r0, 1), "adds pc, r0, #1\n"); in TEST()
2662 COMPARE_A32(Adds(r0, pc, 1), "adds r0, pc, #1\n"); in TEST()
2664 MUST_FAIL_TEST_T32(Adds(r0, pc, 1), "Unpredictable instruction.\n"); in TEST()
2665 MUST_FAIL_TEST_T32(Adds(r0, pc, 0x123), "Ill-formed 'adds' instruction.\n"); in TEST()
2677 COMPARE_A32(Adds(pc, r0, r1), "adds pc, r0, r1\n"); in TEST()
2678 COMPARE_A32(Adds(r in TEST()
[all...]
H A Dtest-assembler-aarch32.cc241 __ Adds(r0, r0, 0); in TEST()
269 __ Adds(r0, r4, r1); in TEST()
295 __ Adds(r0, r0, 0); in TEST()
310 __ Adds(r0, r0, 0); in TEST()
325 __ Adds(r0, r0, 0); in TEST()
340 __ Adds(r0, r0, 0); in TEST()
355 __ Adds(r0, r0, 0); in TEST()
370 __ Adds(r0, r0, 0); in TEST()
385 __ Adds(r0, r1, r2); in TEST()
403 __ Adds(r in TEST()
[all...]
H A Dtest-simulator-cond-rd-rn-operand-rm-a32.cc119 M(Adds) \
H A Dtest-simulator-cond-rd-rn-operand-rm-t32.cc119 M(Adds) \
H A Dtest-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc117 M(Adds) \
H A Dtest-simulator-cond-rd-rn-operand-const-a32.cc119 M(Adds) \
H A Dtest-simulator-cond-rd-rn-operand-const-t32.cc119 M(Adds) \
H A Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc119 M(Adds) \
H A Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc119 M(Adds) \
H A Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc119 M(Adds) \
H A Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc119 M(Adds) \
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMParallelDSP.cpp89 SetVector<Instruction*> Adds; member in __anon24536::Reduction
97 void InsertAdd(Instruction *I) { Adds.insert(I); } in InsertAdd()
120 for (auto *Add : Adds) { in InsertMuls()
169 SetVector<Instruction*> &getAdds() { return Adds; } in getAdds()
186 for (auto *Add : Adds) in dump()
458 // Adds should be adding together two muls, or another add and a mul to in Search()
/third_party/node/deps/v8/tools/vim/
H A Dninja-build.vim5 " Adds a "Compile this file" function, using ninja. On Mac, binds Cmd-k to
9 " Adds a "Build this target" function, using ninja. This is not bound
/third_party/node/deps/v8/src/baseline/arm64/
H A Dbaseline-assembler-arm64-inl.h495 __ Adds(interrupt_budget, interrupt_budget, weight); in AddToInterruptBudgetAndJumpIfNotExceeded()
499 // Use compare flags set by Adds in AddToInterruptBudgetAndJumpIfNotExceeded()
518 __ Adds(interrupt_budget, interrupt_budget, weight.W()); in AddToInterruptBudgetAndJumpIfNotExceeded()
/third_party/node/deps/openssl/openssl/util/perl/OpenSSL/
H A DOrdinals.pm438 Adds a new item from file SOURCE named NAME with the type TYPE,
507 Adds an alias ALIAS for the symbol NAME from file SOURCE, and a set of C macros
/third_party/openssl/util/perl/OpenSSL/
H A DOrdinals.pm438 Adds a new item from file SOURCE named NAME with the type TYPE,
507 Adds an alias ALIAS for the symbol NAME from file SOURCE, and a set of C macros
/third_party/gn/src/gn/
H A Dcommand_gen.cc697 Adds an additional label pattern (see "gn help label_pattern") of a
/third_party/node/deps/v8/src/codegen/arm64/
H A Dmacro-assembler-arm64-inl.h125 void TurboAssembler::Adds(const Register& rd, const Register& rn, in Adds() function in v8::internal::TurboAssembler
160 Adds(AppropriateZeroRegFor(rn), rn, operand); in Cmn()
H A Dmacro-assembler-arm64.h774 inline void Adds(const Register& rd, const Register& rn,
/third_party/vixl/test/aarch64/
H A Dtest-assembler-aarch64.cc66 __ Adds(x3, x0, 0x18001); in TEST()
67 __ Adds(w4, w0, 0xffffff1); in TEST()
87 __ Adds(x14, sp, 0x1f7de); in TEST()
5628 __ Adds(x0, x0, Operand(0));
5693 __ Adds(x0, x0, Operand(0));
5748 __ Adds(x0, x0, Operand(0));
5762 __ Adds(x0, x0, Operand(0));
5775 __ Adds(x0, x0, Operand(0));
5794 __ Adds(x0, x0, Operand(0));
5943 __ Adds(x
[all...]
/third_party/vixl/src/aarch64/
H A Dmacro-assembler-aarch64.cc1504 void MacroAssembler::Adds(const Register& rd, in Emit() function in vixl::aarch64::MacroAssembler
1601 Adds(AppropriateZeroRegFor(rn), rn, operand); in Emit()
/third_party/node/deps/v8/src/compiler/backend/arm64/
H A Dcode-generator-arm64.cc27 // Adds Arm64-specific methods to convert InstructionOperands.
1113 __ Adds(i.OutputRegister(), i.InputOrZeroRegister64(0), in AssembleArchInstruction()
1122 __ Adds(i.OutputRegister32(), i.InputOrZeroRegister32(0), in AssembleArchInstruction()
/third_party/vixl/src/aarch32/
H A Dmacro-assembler-aarch32.h1248 Adds(cond, rd, rn, operand); in MacroAssembler()
1259 Adds(cond, rd, rn, operand); in MacroAssembler()
1283 void Adds(Condition cond, Register rd, Register rn, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
1297 void Adds(Register rd, Register rn, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
1298 Adds(al, rd, rn, operand); in MacroAssembler()
5560 Adds(cond, rd, rn, -operand.GetSignedImmediate()); in MacroAssembler()
/third_party/node/deps/openssl/openssl/crypto/aes/asm/
H A Dvpaes-armv8.pl885 // Adds rcon from low byte of %xmm8, then rotates %xmm8 for
/third_party/openssl/crypto/aes/asm/
H A Dvpaes-armv8.pl904 // Adds rcon from low byte of %xmm8, then rotates %xmm8 for

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