Lines Matching refs:Adds
633 COMPARE_T32(Adds(r0, r0, Operand(r0, ROR, r0)),
1519 COMPARE_A32(Adds(r0, r1, -1), "subs r0, r1, #1\n");
1522 COMPARE_T32(Adds(r0, r1, -1), "adds r0, r1, #4294967295\n");
1525 COMPARE_BOTH(Adds(r0, r1, -4), "subs r0, r1, #4\n");
2661 COMPARE_A32(Adds(pc, r0, 1), "adds pc, r0, #1\n");
2662 COMPARE_A32(Adds(r0, pc, 1), "adds r0, pc, #1\n");
2664 MUST_FAIL_TEST_T32(Adds(r0, pc, 1), "Unpredictable instruction.\n");
2665 MUST_FAIL_TEST_T32(Adds(r0, pc, 0x123), "Ill-formed 'adds' instruction.\n");
2677 COMPARE_A32(Adds(pc, r0, r1), "adds pc, r0, r1\n");
2678 COMPARE_A32(Adds(r0, pc, r1), "adds r0, pc, r1\n");
2679 COMPARE_A32(Adds(r0, r1, pc), "adds r0, r1, pc\n");
2680 MUST_FAIL_TEST_T32(Adds(r0, pc, r1), "Unpredictable instruction.\n");
2681 MUST_FAIL_TEST_T32(Adds(r0, r1, pc), "Unpredictable instruction.\n");
2694 MUST_FAIL_TEST_A32(Adds(pc, r0, Operand(r1, LSL, r2)),
2696 MUST_FAIL_TEST_A32(Adds(r0, pc, Operand(r1, LSL, r2)),
2698 MUST_FAIL_TEST_A32(Adds(r0, r1, Operand(pc, LSL, r2)),
2700 MUST_FAIL_TEST_A32(Adds(r0, r1, Operand(r2, LSL, pc)),
2706 COMPARE_A32(Adds(pc, sp, 1), "adds pc, sp, #1\n");
2707 MUST_FAIL_TEST_T32(Adds(pc, sp, 1), "Ill-formed 'adds' instruction.\n");
2716 COMPARE_A32(Adds(pc, sp, r0), "adds pc, sp, r0\n");
2717 MUST_FAIL_TEST_T32(Adds(pc, sp, r0), "Ill-formed 'adds' instruction.\n");
2718 COMPARE_A32(Adds(r0, sp, pc), "adds r0, sp, pc\n");
2719 MUST_FAIL_TEST_T32(Adds(r0, sp, pc), "Unpredictable instruction.\n");
2720 COMPARE_A32(Adds(pc, sp, pc), "adds pc, sp, pc\n");
2721 MUST_FAIL_TEST_T32(Adds(pc, sp, pc), "Ill-formed 'adds' instruction.\n");
2722 COMPARE_A32(Adds(sp, sp, pc), "adds sp, pc\n");
2723 MUST_FAIL_TEST_T32(Adds(sp, sp, pc), "Unpredictable instruction.\n");