| /third_party/vixl/test/aarch32/ |
| H A D | test-disasm-a32.cc | 624 COMPARE_T32(Adc(r0, r1, Operand(r2, LSL, r3)), in TEST()
1422 COMPARE_BOTH(Adc(r0, r1, 0xbadbeef), in TEST()
1527 COMPARE_BOTH(Adc(r0, r1, -2), "sbc r0, r1, #1\n"); in TEST()
1544 COMPARE_BOTH(Adc(r0, r1, 0xabcd), in TEST()
1548 COMPARE_BOTH(Adc(r0, r1, -0xabcd), in TEST()
1552 COMPARE_BOTH(Adc(r0, r1, 0x1234abcd), in TEST()
1557 COMPARE_BOTH(Adc(r0, r1, -0x1234abcd), in TEST()
1585 COMPARE_T32(Adc(r0, r1, Operand(r2, LSL, r3)), in TEST()
2610 COMPARE_A32(Adc(pc, r0, 1), "adc pc, r0, #1\n"); in TEST()
2611 COMPARE_A32(Adc(r in TEST()
[all...] |
| H A D | test-assembler-aarch32.cc | 243 __ Adc(r4, r2, r3); in TEST()
244 __ Adc(r5, r0, Operand(r1, LSL, 30)); in TEST()
245 __ Adc(r6, r0, Operand(r2, LSR, 16)); in TEST()
246 __ Adc(r7, r2, Operand(r3, ASR, 4)); in TEST()
247 __ Adc(r8, r2, Operand(r3, ROR, 8)); in TEST()
248 __ Adc(r9, r2, Operand(r3, RRX)); in TEST()
271 __ Adc(r5, r2, r3); in TEST()
272 __ Adc(r6, r0, Operand(r1, LSL, 30)); in TEST()
273 __ Adc(r7, r0, Operand(r2, LSR, 16)); in TEST()
274 __ Adc(r in TEST()
[all...] |
| H A D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 116 M(Adc) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 116 M(Adc) \
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| H A D | test-simulator-cond-rd-rn-operand-const-a32.cc | 116 M(Adc) \
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| H A D | test-simulator-cond-rd-rn-operand-const-t32.cc | 116 M(Adc) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 116 M(Adc) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 116 M(Adc) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 116 M(Adc) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 116 M(Adc) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 116 M(Adc) \
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| /third_party/vixl/test/aarch64/ |
| H A D | test-assembler-aarch64.cc | 5630 __ Adc(x5, x2, Operand(x3));
5631 __ Adc(x6, x0, Operand(x1, LSL, 60));
5633 __ Adc(x8, x2, Operand(x3, ASR, 4));
5634 __ Adc(x9, x2, Operand(x3, ROR, 8));
5636 __ Adc(w10, w2, Operand(w3));
5637 __ Adc(w11, w0, Operand(w1, LSL, 30));
5639 __ Adc(w13, w2, Operand(w3, ASR, 4));
5640 __ Adc(w14, w2, Operand(w3, ROR, 8));
5645 __ Adc(x18, x2, Operand(x3));
5646 __ Adc(x1
[all...] |
| H A D | test-disasm-aarch64.cc | 2880 // Adc and Sbc use their destination register as a scratch if they can. in TEST()
2881 COMPARE_MACRO(Adc(x0, x1, 0x4242), in TEST()
2884 COMPARE_MACRO(Adc(x0, x0, 0x4242), in TEST()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| H A D | IceInstX8632.h | 192 Adc, enumerator
1424 class InstX86Adc : public InstX86BaseBinopGPR<InstX86Base::Adc> {
1432 : InstX86BaseBinopGPR<InstX86Base::Adc>(Func, Dest, Source) {} in InstX86Adc()
3185 using Adc = InstX86Adc;
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| H A D | IceInstX8664.h | 133 Adc, enumerator
1365 class InstX86Adc : public InstX86BaseBinopGPR<InstX86Base::Adc> {
1373 : InstX86BaseBinopGPR<InstX86Base::Adc>(Func, Dest, Source) {} in InstX86Adc()
3084 using Adc = InstX86Adc;
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| H A D | IceInstARM32.h | 380 Adc, enumerator
1002 using InstARM32Adc = InstARM32ThreeAddrGPR<InstARM32::Adc>;
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| H A D | IceTargetLoweringX8632.h | 445 Context.insert<Insts::Adc>(Dest, Src0);
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| H A D | IceTargetLoweringX8664.h | 441 Context.insert<Insts::Adc>(Dest, Src0);
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| H A D | IceInstARM32.cpp | 3405 template class InstARM32ThreeAddrGPR<InstARM32::Adc>;
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64-inl.h | 191 void TurboAssembler::Adc(const Register& rd, const Register& rn, in Adc() function in v8::internal::TurboAssembler
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| H A D | macro-assembler-arm64.h | 1093 inline void Adc(const Register& rd, const Register& rn,
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| /third_party/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.h | 1125 void Adc(Condition cond, Register rd, Register rn, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
1143 void Adc(Register rd, Register rn, const Operand& operand) { in MacroAssembler() function in vixl::aarch32::MacroAssembler
1144 Adc(al, rd, rn, operand); in MacroAssembler()
1146 void Adc(FlagsUpdate flags, in MacroAssembler() function in vixl::aarch32::MacroAssembler
1153 Adc(cond, rd, rn, operand); in MacroAssembler()
1165 Adc(cond, rd, rn, operand); in MacroAssembler()
1170 void Adc(FlagsUpdate flags, in MacroAssembler() function in vixl::aarch32::MacroAssembler
1174 Adc(flags, al, rd, rn, operand); in MacroAssembler()
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.cc | 1941 void MacroAssembler::Adc(const Register& rd, in Emit() function in vixl::aarch64::MacroAssembler
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| H A D | macro-assembler-aarch64.h | 828 void Adc(const Register& rd, const Register& rn, const Operand& operand);
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| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| H A D | code-generator-arm64.cc | 1738 __ Adc(i.OutputRegister32(), i.OutputRegister32(), Operand(0)); in AssembleArchInstruction()
|