Lines Matching refs:Adc
624 COMPARE_T32(Adc(r0, r1, Operand(r2, LSL, r3)),
1422 COMPARE_BOTH(Adc(r0, r1, 0xbadbeef),
1527 COMPARE_BOTH(Adc(r0, r1, -2), "sbc r0, r1, #1\n");
1544 COMPARE_BOTH(Adc(r0, r1, 0xabcd),
1548 COMPARE_BOTH(Adc(r0, r1, -0xabcd),
1552 COMPARE_BOTH(Adc(r0, r1, 0x1234abcd),
1557 COMPARE_BOTH(Adc(r0, r1, -0x1234abcd),
1585 COMPARE_T32(Adc(r0, r1, Operand(r2, LSL, r3)),
2610 COMPARE_A32(Adc(pc, r0, 1), "adc pc, r0, #1\n");
2611 COMPARE_A32(Adc(r0, pc, 1), "adc r0, pc, #1\n");
2612 MUST_FAIL_TEST_T32(Adc(pc, r0, 1), "Unpredictable instruction.\n");
2613 MUST_FAIL_TEST_T32(Adc(r0, pc, 1), "Unpredictable instruction.\n");
2620 COMPARE_A32(Adc(pc, r0, r1), "adc pc, r0, r1\n");
2621 COMPARE_A32(Adc(r0, pc, r1), "adc r0, pc, r1\n");
2622 COMPARE_A32(Adc(r0, r1, pc), "adc r0, r1, pc\n");
2623 MUST_FAIL_TEST_T32(Adc(pc, r0, r1), "Unpredictable instruction.\n");
2624 MUST_FAIL_TEST_T32(Adc(r0, pc, r1), "Unpredictable instruction.\n");
2625 MUST_FAIL_TEST_T32(Adc(r0, r1, pc), "Unpredictable instruction.\n");
2634 MUST_FAIL_TEST_A32(Adc(pc, r0, Operand(r1, LSL, r2)),
2636 MUST_FAIL_TEST_A32(Adc(r0, pc, Operand(r1, LSL, r2)),
2638 MUST_FAIL_TEST_A32(Adc(r0, r1, Operand(pc, LSL, r2)),
2640 MUST_FAIL_TEST_A32(Adc(r0, r1, Operand(r2, LSL, pc)),
3197 COMPARE_T32(Adc(eq, r0, r0, r1),
3201 COMPARE_T32(Adc(eq, r0, r1, r2),
3975 CHECK_T32_16(Adc(DontCare, r7, r7, r6), "adcs r7, r6\n");
3977 CHECK_T32_16_IT_BLOCK(Adc(DontCare, eq, r7, r7, r6),