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Searched refs:wrmsrl (Results 1 - 25 of 157) sorted by relevance

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/kernel/linux/linux-5.10/arch/x86/hyperv/
H A Dhv_init.c114 wrmsrl(HV_X64_MSR_VP_ASSIST_PAGE, val); in hv_cpu_init()
141 wrmsrl(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status); in hyperv_stop_tsc_emulation()
189 wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); in set_hv_tscchange_cb()
190 wrmsrl(HV_X64_MSR_TSC_EMULATION_CONTROL, *((u64 *)&emu_ctrl)); in set_hv_tscchange_cb()
205 wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *(u64 *)&re_ctrl); in clear_hv_tscchange_cb()
227 wrmsrl(HV_X64_MSR_VP_ASSIST_PAGE, 0); in hv_cpu_die()
246 wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); in hv_cpu_die()
286 wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); in hv_suspend()
305 wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); in hv_resume()
404 wrmsrl(HV_X64_MSR_GUEST_OS_I in hyperv_init()
[all...]
/kernel/linux/linux-6.6/arch/x86/hyperv/
H A Dhv_init.c136 wrmsrl(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64); in hv_cpu_init()
163 wrmsrl(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status); in hyperv_stop_tsc_emulation()
211 wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); in set_hv_tscchange_cb()
212 wrmsrl(HV_X64_MSR_TSC_EMULATION_CONTROL, *((u64 *)&emu_ctrl)); in set_hv_tscchange_cb()
227 wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *(u64 *)&re_ctrl); in clear_hv_tscchange_cb()
262 wrmsrl(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64); in hv_cpu_die()
282 wrmsrl(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); in hv_cpu_die()
341 wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); in hv_suspend()
360 wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); in hv_resume()
525 wrmsrl(HV_X64_MSR_GUEST_OS_I in hyperv_init()
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/kernel/linux/linux-5.10/arch/x86/events/intel/
H A Duncore_nhmex.c202 wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, NHMEX_U_PMON_GLOBAL_EN_ALL); in nhmex_uncore_msr_init_box()
207 wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, 0); in nhmex_uncore_msr_exit_box()
221 wrmsrl(msr, config); in nhmex_uncore_msr_disable_box()
236 wrmsrl(msr, config); in nhmex_uncore_msr_enable_box()
242 wrmsrl(event->hw.config_base, 0); in nhmex_uncore_msr_disable_event()
250 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
252 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); in nhmex_uncore_msr_enable_event()
254 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
384 wrmsrl(reg1->reg, reg1->config); in nhmex_bbox_msr_enable_event()
385 wrmsrl(reg in nhmex_bbox_msr_enable_event()
[all...]
/kernel/linux/linux-6.6/arch/x86/events/intel/
H A Duncore_nhmex.c202 wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, NHMEX_U_PMON_GLOBAL_EN_ALL); in nhmex_uncore_msr_init_box()
207 wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, 0); in nhmex_uncore_msr_exit_box()
221 wrmsrl(msr, config); in nhmex_uncore_msr_disable_box()
236 wrmsrl(msr, config); in nhmex_uncore_msr_enable_box()
242 wrmsrl(event->hw.config_base, 0); in nhmex_uncore_msr_disable_event()
250 wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
252 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); in nhmex_uncore_msr_enable_event()
254 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
384 wrmsrl(reg1->reg, reg1->config); in nhmex_bbox_msr_enable_event()
385 wrmsrl(reg in nhmex_bbox_msr_enable_event()
[all...]
H A Duncore_snb.c262 wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); in snb_uncore_msr_enable_event()
264 wrmsrl(hwc->config_base, SNB_UNC_CTL_EN); in snb_uncore_msr_enable_event()
269 wrmsrl(event->hw.config_base, 0); in snb_uncore_msr_disable_event()
275 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, in snb_uncore_msr_init_box()
282 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, in snb_uncore_msr_enable_box()
289 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, 0); in snb_uncore_msr_exit_box()
374 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, in skl_uncore_msr_init_box()
385 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, in skl_uncore_msr_enable_box()
392 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 0); in skl_uncore_msr_exit_box()
527 wrmsrl(SKL_UNC_PERF_GLOBAL_CT in rkl_uncore_msr_init_box()
[all...]
/kernel/linux/linux-5.10/arch/x86/include/asm/
H A Dmshyperv.h18 wrmsrl(HV_X64_MSR_STIMER0_COUNT + (2*timer), tick)
20 wrmsrl(HV_X64_MSR_STIMER0_CONFIG + (2*timer), val)
23 #define hv_set_simp(val) wrmsrl(HV_X64_MSR_SIMP, val)
26 #define hv_set_siefp(val) wrmsrl(HV_X64_MSR_SIEFP, val)
29 #define hv_set_synic_state(val) wrmsrl(HV_X64_MSR_SCONTROL, val)
33 #define hv_signal_eom() wrmsrl(HV_X64_MSR_EOM, 0)
38 wrmsrl(HV_X64_MSR_SINT0 + int_num, val)
51 wrmsrl(HV_X64_MSR_REFERENCE_TSC, val)
H A Dvirtext.h115 wrmsrl(MSR_VM_HSAVE_PA, 0); in cpu_svm_disable()
130 wrmsrl(MSR_EFER, efer & ~EFER_SVME); in cpu_svm_disable()
/kernel/linux/linux-5.10/arch/x86/oprofile/
H A Dop_model_amd.c156 wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl); in op_amd_handle_ibs()
185 wrmsrl(MSR_AMD64_IBSOPCTL, ctl); in op_amd_handle_ibs()
211 wrmsrl(MSR_AMD64_IBSFETCHCTL, val); in op_amd_start_ibs()
248 wrmsrl(MSR_AMD64_IBSOPCTL, val); in op_amd_start_ibs()
259 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0); in op_amd_stop_ibs()
263 wrmsrl(MSR_AMD64_IBSOPCTL, 0); in op_amd_stop_ibs()
282 wrmsrl(msrs->controls[i].addr, val); in op_mux_switch_ctrl()
356 wrmsrl(msrs->controls[i].addr, val); in op_amd_setup_ctrs()
361 wrmsrl(msrs->counters[i].addr, -1LL); in op_amd_setup_ctrs()
371 wrmsrl(msr in op_amd_setup_ctrs()
[all...]
H A Dop_model_ppro.c103 wrmsrl(msrs->controls[i].addr, val); in ppro_setup_ctrs()
108 wrmsrl(msrs->counters[i].addr, -1LL); in ppro_setup_ctrs()
115 wrmsrl(msrs->counters[i].addr, -reset_value[i]); in ppro_setup_ctrs()
119 wrmsrl(msrs->controls[i].addr, val); in ppro_setup_ctrs()
140 wrmsrl(msrs->counters[i].addr, -reset_value[i]); in ppro_check_ctrs()
167 wrmsrl(msrs->controls[i].addr, val); in ppro_start()
183 wrmsrl(msrs->controls[i].addr, val); in ppro_stop()
/kernel/linux/linux-6.6/arch/x86/kernel/cpu/
H A Dtsx.c40 wrmsrl(MSR_IA32_TSX_CTRL, tsx); in tsx_disable()
59 wrmsrl(MSR_IA32_TSX_CTRL, tsx); in tsx_enable()
120 wrmsrl(MSR_TSX_FORCE_ABORT, msr); in tsx_clear_cpuid()
124 wrmsrl(MSR_IA32_TSX_CTRL, msr); in tsx_clear_cpuid()
153 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_opt_ctrl); in tsx_dev_mode_disable()
/kernel/linux/linux-6.6/arch/x86/events/amd/
H A Dlbr.c64 wrmsrl(MSR_AMD_SAMP_BR_FROM + idx * 2, val); in amd_pmu_lbr_set_from()
69 wrmsrl(MSR_AMD_SAMP_BR_FROM + idx * 2 + 1, val); in amd_pmu_lbr_set_to()
338 wrmsrl(MSR_AMD64_LBR_SELECT, 0); in amd_pmu_lbr_reset()
400 wrmsrl(MSR_AMD64_LBR_SELECT, lbr_select); in amd_pmu_lbr_enable_all()
406 wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); in amd_pmu_lbr_enable_all()
407 wrmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg | DBG_EXTN_CFG_LBRV2EN); in amd_pmu_lbr_enable_all()
421 wrmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN); in amd_pmu_lbr_disable_all()
422 wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); in amd_pmu_lbr_disable_all()
/kernel/linux/linux-6.6/arch/x86/kernel/
H A Dkvm.c302 wrmsrl(MSR_KVM_ASYNC_PF_ACK, 1); in DEFINE_IDTENTRY_SYSVEC()
328 wrmsrl(MSR_KVM_STEAL_TIME, (slow_virt_to_phys(st) | KVM_MSR_ENABLED)); in kvm_register_steal_time()
362 wrmsrl(MSR_KVM_ASYNC_PF_INT, HYPERVISOR_CALLBACK_VECTOR); in kvm_guest_cpu_init()
364 wrmsrl(MSR_KVM_ASYNC_PF_EN, pa); in kvm_guest_cpu_init()
377 wrmsrl(MSR_KVM_PV_EOI_EN, pa); in kvm_guest_cpu_init()
389 wrmsrl(MSR_KVM_ASYNC_PF_EN, 0); in kvm_pv_disable_apf()
451 wrmsrl(MSR_KVM_PV_EOI_EN, 0); in kvm_guest_cpu_offline()
453 wrmsrl(MSR_KVM_MIGRATION_CONTROL, 0); in kvm_guest_cpu_offline()
615 wrmsrl(MSR_KVM_MIGRATION_CONTROL, KVM_MIGRATION_READY); in setup_efi_kvm_sev_migration()
740 wrmsrl(MSR_KVM_POLL_CONTRO in kvm_resume()
[all...]
H A Dshstk.c176 wrmsrl(MSR_IA32_PL3_SSP, addr + size); in shstk_setup()
177 wrmsrl(MSR_IA32_U_CET, CET_SHSTK_EN); in shstk_setup()
375 wrmsrl(MSR_IA32_PL3_SSP, ssp); in setup_signal_shadow_stack()
399 wrmsrl(MSR_IA32_PL3_SSP, ssp); in restore_signal_shadow_stack()
476 wrmsrl(MSR_IA32_U_CET, msrval); in wrss_control()
495 wrmsrl(MSR_IA32_U_CET, 0); in shstk_disable()
496 wrmsrl(MSR_IA32_PL3_SSP, 0); in shstk_disable()
H A Dtsc_sync.c73 wrmsrl(MSR_IA32_TSC_ADJUST, adj->adjusted); in tsc_verify_tsc_adjust()
145 wrmsrl(MSR_IA32_TSC_ADJUST, 0); in tsc_sanitize_first_cpu()
234 wrmsrl(MSR_IA32_TSC_ADJUST, ref->adjusted); in tsc_store_and_check_tsc_adjust()
523 wrmsrl(MSR_IA32_TSC_ADJUST, cur->adjusted); in check_tsc_sync_target()
/kernel/linux/linux-5.10/arch/x86/kernel/cpu/mce/
H A Dinject.c462 wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); in prepare_msrs()
466 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); in prepare_msrs()
467 wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); in prepare_msrs()
469 wrmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); in prepare_msrs()
470 wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); in prepare_msrs()
473 wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); in prepare_msrs()
474 wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); in prepare_msrs()
476 wrmsrl(MSR_IA32_MCx_STATUS(b), m.status); in prepare_msrs()
477 wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr); in prepare_msrs()
478 wrmsrl(MSR_IA32_MCx_MIS in prepare_msrs()
[all...]
H A Dintel.c171 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); in cmci_toggle_interrupt_mode()
309 wrmsrl(MSR_IA32_MCx_CTL2(i), val); in cmci_discover()
364 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); in __cmci_disable_bank()
458 wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN); in intel_init_lmce()
470 wrmsrl(MSR_IA32_MCG_EXT_CTL, val); in intel_clear_lmce()
/kernel/linux/linux-5.10/arch/x86/kernel/
H A Dkvm.c300 wrmsrl(MSR_KVM_ASYNC_PF_ACK, 1); in DEFINE_IDTENTRY_SYSVEC()
326 wrmsrl(MSR_KVM_STEAL_TIME, (slow_virt_to_phys(st) | KVM_MSR_ENABLED)); in kvm_register_steal_time()
360 wrmsrl(MSR_KVM_ASYNC_PF_INT, HYPERVISOR_CALLBACK_VECTOR); in kvm_guest_cpu_init()
362 wrmsrl(MSR_KVM_ASYNC_PF_EN, pa); in kvm_guest_cpu_init()
375 wrmsrl(MSR_KVM_PV_EOI_EN, pa); in kvm_guest_cpu_init()
387 wrmsrl(MSR_KVM_ASYNC_PF_EN, 0); in kvm_pv_disable_apf()
409 wrmsrl(MSR_KVM_PV_EOI_EN, 0); in kvm_pv_guest_cpu_reboot()
483 wrmsrl(MSR_KVM_PV_EOI_EN, 0); in kvm_guest_cpu_offline()
659 wrmsrl(MSR_KVM_POLL_CONTROL, 0); in kvm_resume()
1024 wrmsrl(MSR_KVM_POLL_CONTRO in kvm_disable_host_haltpoll()
[all...]
H A Dtsc_sync.c72 wrmsrl(MSR_IA32_TSC_ADJUST, adj->adjusted); in tsc_verify_tsc_adjust()
144 wrmsrl(MSR_IA32_TSC_ADJUST, 0); in tsc_sanitize_first_cpu()
233 wrmsrl(MSR_IA32_TSC_ADJUST, ref->adjusted); in tsc_store_and_check_tsc_adjust()
529 wrmsrl(MSR_IA32_TSC_ADJUST, cur->adjusted); in check_tsc_sync_target()
/kernel/linux/linux-5.10/arch/x86/power/
H A Dcpu.c57 wrmsrl(msr->info.msr_no, msr->info.reg.q); in msr_restore_context()
201 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable); in __restore_processor_state()
211 wrmsrl(MSR_EFER, ctxt->efer); in __restore_processor_state()
234 wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base); in __restore_processor_state()
258 wrmsrl(MSR_FS_BASE, ctxt->fs_base); in __restore_processor_state()
259 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base); in __restore_processor_state()
/kernel/linux/linux-6.6/arch/x86/power/
H A Dcpu.c58 wrmsrl(msr->info.msr_no, msr->info.reg.q); in msr_restore_context()
200 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable); in __restore_processor_state()
210 wrmsrl(MSR_EFER, ctxt->efer); in __restore_processor_state()
233 wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base); in __restore_processor_state()
256 wrmsrl(MSR_FS_BASE, ctxt->fs_base); in __restore_processor_state()
257 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base); in __restore_processor_state()
/kernel/linux/linux-6.6/arch/x86/kernel/cpu/mce/
H A Dinject.c481 wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); in prepare_msrs()
485 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); in prepare_msrs()
486 wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); in prepare_msrs()
488 wrmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); in prepare_msrs()
489 wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); in prepare_msrs()
492 wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); in prepare_msrs()
493 wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); in prepare_msrs()
495 wrmsrl(MSR_IA32_MCx_STATUS(b), m.status); in prepare_msrs()
496 wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr); in prepare_msrs()
497 wrmsrl(MSR_IA32_MCx_MIS in prepare_msrs()
[all...]
H A Dintel.c178 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); in cmci_toggle_interrupt_mode()
316 wrmsrl(MSR_IA32_MCx_CTL2(i), val); in cmci_discover()
371 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); in __cmci_disable_bank()
475 wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN); in intel_init_lmce()
487 wrmsrl(MSR_IA32_MCG_EXT_CTL, val); in intel_clear_lmce()
/kernel/linux/linux-5.10/arch/x86/kernel/cpu/
H A Dtsx.c39 wrmsrl(MSR_IA32_TSX_CTRL, tsx); in tsx_disable()
58 wrmsrl(MSR_IA32_TSX_CTRL, tsx); in tsx_enable()
/kernel/linux/linux-5.10/arch/x86/xen/
H A Dsuspend.c44 wrmsrl(MSR_IA32_SPEC_CTRL, this_cpu_read(spec_ctrl)); in xen_vcpu_notify_restore()
62 wrmsrl(MSR_IA32_SPEC_CTRL, 0); in xen_vcpu_notify_suspend()
/kernel/linux/linux-6.6/arch/x86/xen/
H A Dsuspend.c44 wrmsrl(MSR_IA32_SPEC_CTRL, this_cpu_read(spec_ctrl)); in xen_vcpu_notify_restore()
62 wrmsrl(MSR_IA32_SPEC_CTRL, 0); in xen_vcpu_notify_suspend()

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