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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_vce.c90 * amdgpu_vce_init - allocate memory, load vce firmware
159 r = request_firmware(&adev->vce.fw, fw_name, adev->dev); in amdgpu_vce_sw_init()
166 r = amdgpu_ucode_validate(adev->vce.fw); in amdgpu_vce_sw_init()
170 release_firmware(adev->vce.fw); in amdgpu_vce_sw_init()
171 adev->vce.fw = NULL; in amdgpu_vce_sw_init()
175 hdr = (const struct common_firmware_header *)adev->vce.fw->data; in amdgpu_vce_sw_init()
183 adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) | in amdgpu_vce_sw_init()
187 AMDGPU_GEM_DOMAIN_VRAM, &adev->vce.vcpu_bo, in amdgpu_vce_sw_init()
188 &adev->vce.gpu_addr, &adev->vce in amdgpu_vce_sw_init()
[all...]
H A Dvce_v3_0.c33 #include "vce/vce_3_0_d.h"
34 #include "vce/vce_3_0_sh_mask.h"
83 if (adev->vce.harvest_config == 0 || in vce_v3_0_ring_get_rptr()
84 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1) in vce_v3_0_ring_get_rptr()
86 else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) in vce_v3_0_ring_get_rptr()
115 if (adev->vce.harvest_config == 0 || in vce_v3_0_ring_get_wptr()
116 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1) in vce_v3_0_ring_get_wptr()
118 else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) in vce_v3_0_ring_get_wptr()
146 if (adev->vce.harvest_config == 0 || in vce_v3_0_ring_set_wptr()
147 adev->vce in vce_v3_0_ring_set_wptr()
[all...]
H A Dvce_v4_0.c36 #include "vce/vce_4_0_offset.h"
37 #include "vce/vce_4_0_default.h"
38 #include "vce/vce_4_0_sh_mask.h"
42 #include "ivsrcid/vce/irqsrcs_vce_4_0.h"
178 WDOORBELL32(adev->vce.ring[0].doorbell_index, 0); in vce_v4_0_mmsch_start()
179 adev->wb.wb[adev->vce.ring[0].wptr_offs] = 0; in vce_v4_0_mmsch_start()
180 adev->vce.ring[0].wptr = 0; in vce_v4_0_mmsch_start()
181 adev->vce.ring[0].wptr_old = 0; in vce_v4_0_mmsch_start()
232 ring = &adev->vce.ring[0]; in vce_v4_0_sriov_start()
262 adev->vce in vce_v4_0_sriov_start()
[all...]
H A Dvce_v2_0.c33 #include "vce/vce_2_0_d.h"
34 #include "vce/vce_2_0_sh_mask.h"
183 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); in vce_v2_0_mc_resume()
243 ring = &adev->vce.ring[0]; in vce_v2_0_start()
250 ring = &adev->vce.ring[1]; in vce_v2_0_start()
281 DRM_INFO("vce is not idle \n"); in vce_v2_0_stop()
405 adev->vce.num_rings = 2; in vce_v2_0_early_init()
420 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 167, &adev->vce.irq); in vce_v2_0_sw_init()
433 for (i = 0; i < adev->vce.num_rings; i++) { in vce_v2_0_sw_init()
434 ring = &adev->vce in vce_v2_0_sw_init()
[all...]
H A Damdgpu_kms.c227 fw_info->ver = adev->vce.fw_version; in amdgpu_firmware_info()
228 fw_info->feature = adev->vce.fb_version; in amdgpu_firmware_info()
386 for (i = 0; i < adev->vce.num_rings; i++) in amdgpu_hw_ip_info()
387 if (adev->vce.ring[i].sched.ready) in amdgpu_hw_ip_info()
759 if (adev->vce.fw_version && in amdgpu_info_ioctl()
760 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) in amdgpu_info_ioctl()
783 dev_info.vce_harvest_config = adev->vce.harvest_config; in amdgpu_info_ioctl()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_vce.c91 * amdgpu_vce_sw_init - allocate memory, load vce firmware
161 r = amdgpu_ucode_request(adev, &adev->vce.fw, fw_name); in amdgpu_vce_sw_init()
165 amdgpu_ucode_release(&adev->vce.fw); in amdgpu_vce_sw_init()
169 hdr = (const struct common_firmware_header *)adev->vce.fw->data; in amdgpu_vce_sw_init()
177 adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) | in amdgpu_vce_sw_init()
183 &adev->vce.vcpu_bo, in amdgpu_vce_sw_init()
184 &adev->vce.gpu_addr, &adev->vce.cpu_addr); in amdgpu_vce_sw_init()
191 atomic_set(&adev->vce.handles[i], 0); in amdgpu_vce_sw_init()
192 adev->vce in amdgpu_vce_sw_init()
[all...]
H A Dvce_v3_0.c33 #include "vce/vce_3_0_d.h"
34 #include "vce/vce_3_0_sh_mask.h"
83 if (adev->vce.harvest_config == 0 || in vce_v3_0_ring_get_rptr()
84 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1) in vce_v3_0_ring_get_rptr()
86 else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) in vce_v3_0_ring_get_rptr()
115 if (adev->vce.harvest_config == 0 || in vce_v3_0_ring_get_wptr()
116 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1) in vce_v3_0_ring_get_wptr()
118 else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) in vce_v3_0_ring_get_wptr()
146 if (adev->vce.harvest_config == 0 || in vce_v3_0_ring_set_wptr()
147 adev->vce in vce_v3_0_ring_set_wptr()
[all...]
H A Dvce_v4_0.c37 #include "vce/vce_4_0_offset.h"
38 #include "vce/vce_4_0_default.h"
39 #include "vce/vce_4_0_sh_mask.h"
43 #include "ivsrcid/vce/irqsrcs_vce_4_0.h"
179 WDOORBELL32(adev->vce.ring[0].doorbell_index, 0); in vce_v4_0_mmsch_start()
180 *adev->vce.ring[0].wptr_cpu_addr = 0; in vce_v4_0_mmsch_start()
181 adev->vce.ring[0].wptr = 0; in vce_v4_0_mmsch_start()
182 adev->vce.ring[0].wptr_old = 0; in vce_v4_0_mmsch_start()
233 ring = &adev->vce.ring[0]; in vce_v4_0_sriov_start()
263 adev->vce in vce_v4_0_sriov_start()
[all...]
H A Dvce_v2_0.c33 #include "vce/vce_2_0_d.h"
34 #include "vce/vce_2_0_sh_mask.h"
183 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); in vce_v2_0_mc_resume()
243 ring = &adev->vce.ring[0]; in vce_v2_0_start()
250 ring = &adev->vce.ring[1]; in vce_v2_0_start()
281 DRM_INFO("vce is not idle \n"); in vce_v2_0_stop()
405 adev->vce.num_rings = 2; in vce_v2_0_early_init()
420 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 167, &adev->vce.irq); in vce_v2_0_sw_init()
433 for (i = 0; i < adev->vce.num_rings; i++) { in vce_v2_0_sw_init()
436 ring = &adev->vce in vce_v2_0_sw_init()
[all...]
H A Damdgpu_kms.c209 fw_info->ver = adev->vce.fw_version; in amdgpu_firmware_info()
210 fw_info->feature = adev->vce.fb_version; in amdgpu_firmware_info()
413 for (i = 0; i < adev->vce.num_rings; i++) in amdgpu_hw_ip_info()
414 if (adev->vce.ring[i].sched.ready) in amdgpu_hw_ip_info()
821 if (adev->vce.fw_version && in amdgpu_info_ioctl()
822 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) in amdgpu_info_ioctl()
845 dev_info->vce_harvest_config = adev->vce.harvest_config; in amdgpu_info_ioctl()
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Dradeon_vce.c50 * radeon_vce_init - allocate memory, load vce firmware
65 INIT_DELAYED_WORK(&rdev->vce.idle_work, radeon_vce_idle_work_handler); in radeon_vce_init()
121 if (sscanf(c, "%2u]", &rdev->vce.fb_version) != 1) in radeon_vce_init()
125 start, mid, end, rdev->vce.fb_version); in radeon_vce_init()
127 rdev->vce.fw_version = (start << 24) | (mid << 16) | (end << 8); in radeon_vce_init()
130 if ((rdev->vce.fw_version != ((40 << 24) | (2 << 16) | (2 << 8))) && in radeon_vce_init()
131 (rdev->vce.fw_version != ((50 << 24) | (0 << 16) | (1 << 8))) && in radeon_vce_init()
132 (rdev->vce.fw_version != ((50 << 24) | (1 << 16) | (2 << 8)))) in radeon_vce_init()
143 &rdev->vce.vcpu_bo); in radeon_vce_init()
149 r = radeon_bo_reserve(rdev->vce in radeon_vce_init()
[all...]
H A Dvce_v1_0.c204 rdev->vce.keyselect = le32_to_cpu(sign->val[i].keyselect); in vce_v1_0_load_fw()
217 uint64_t addr = rdev->vce.gpu_addr; in vce_v1_0_resume()
253 WREG32(VCE_LMI_FW_START_KEYSEL, rdev->vce.keyselect); in vce_v1_0_resume()
H A Dvce_v2_0.c159 uint64_t addr = rdev->vce.gpu_addr; in vce_v2_0_resume()
H A Dradeon_drv.c296 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
297 module_param_named(vce, radeon_vce, int, 0444);
H A Dradeon_kms.c526 *value = rdev->vce.fw_version; in radeon_info_ioctl()
529 *value = rdev->vce.fb_version; in radeon_info_ioctl()
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Dradeon_vce.c50 * radeon_vce_init - allocate memory, load vce firmware
65 INIT_DELAYED_WORK(&rdev->vce.idle_work, radeon_vce_idle_work_handler); in radeon_vce_init()
121 if (sscanf(c, "%2u]", &rdev->vce.fb_version) != 1) in radeon_vce_init()
125 start, mid, end, rdev->vce.fb_version); in radeon_vce_init()
127 rdev->vce.fw_version = (start << 24) | (mid << 16) | (end << 8); in radeon_vce_init()
130 if ((rdev->vce.fw_version != ((40 << 24) | (2 << 16) | (2 << 8))) && in radeon_vce_init()
131 (rdev->vce.fw_version != ((50 << 24) | (0 << 16) | (1 << 8))) && in radeon_vce_init()
132 (rdev->vce.fw_version != ((50 << 24) | (1 << 16) | (2 << 8)))) in radeon_vce_init()
143 &rdev->vce.vcpu_bo); in radeon_vce_init()
149 r = radeon_bo_reserve(rdev->vce in radeon_vce_init()
[all...]
H A Dvce_v1_0.c33 #include "vce.h"
205 rdev->vce.keyselect = le32_to_cpu(sign->val[i].keyselect); in vce_v1_0_load_fw()
218 uint64_t addr = rdev->vce.gpu_addr; in vce_v1_0_resume()
254 WREG32(VCE_LMI_FW_START_KEYSEL, rdev->vce.keyselect); in vce_v1_0_resume()
H A Dvce_v2_0.c33 #include "vce.h"
160 uint64_t addr = rdev->vce.gpu_addr; in vce_v2_0_resume()
H A Dradeon_drv.c239 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
240 module_param_named(vce, radeon_vce, int, 0444);
H A Dradeon_kms.c540 *value = rdev->vce.fw_version; in radeon_info_ioctl()
543 *value = rdev->vce.fb_version; in radeon_info_ioctl()
/kernel/linux/linux-6.6/arch/s390/kernel/
H A Dcert_store.c127 struct vce { struct
178 static void pr_dbf_vce(const struct vce *e) in pr_dbf_vce()
259 static int check_certificate_hash(const struct vce *vce) in check_certificate_hash() argument
265 vce_hash = (u8 *)vce + vce->vce_hdr.vc_hash_offset; in check_certificate_hash()
266 vc_hash_length = vce->vce_hdr.vc_hash_length; in check_certificate_hash()
267 sha256((u8 *)vce + vce->vce_hdr.vc_offset, vce in check_certificate_hash()
280 check_certificate_valid(const struct vce *vce) check_certificate_valid() argument
428 get_key_description(struct vcssb *vcssb, const struct vce *vce) get_key_description() argument
453 create_key_from_vce(struct vcssb *vcssb, struct vce *vce, struct key *keyring) create_key_from_vce() argument
523 extract_vce_from_sevcb(struct vcb *vcb, struct vce *vce) extract_vce_from_sevcb() argument
575 struct vce *vce; create_key_from_sevcb() local
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu8_hwmgr.h134 uint32_t vce : 1; member
H A Dsmu10_hwmgr.h111 uint32_t vce : 1; member
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu10_hwmgr.h111 uint32_t vce : 1; member
H A Dsmu8_hwmgr.h134 uint32_t vce : 1; member

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