| /kernel/linux/linux-5.10/drivers/clk/mediatek/ |
| H A D | clk-mt8183-ipu_conn.c | 15 .set_ofs = 0x4,
21 .set_ofs = 0x10,
27 .set_ofs = 0x18,
33 .set_ofs = 0x1c,
39 .set_ofs = 0x20,
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| H A D | clk-mt2701-aud.c | 55 .set_ofs = 0x0,
61 .set_ofs = 0x10,
67 .set_ofs = 0x14,
73 .set_ofs = 0x634,
|
| H A D | clk-gate.c | 46 regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit)); in mtk_cg_set_bit()
148 int set_ofs, in mtk_clk_register_gate()
171 cg->set_ofs = set_ofs; in mtk_clk_register_gate()
144 mtk_clk_register_gate( const char *name, const char *parent_name, struct regmap *regmap, int set_ofs, int clr_ofs, int sta_ofs, u8 bit, const struct clk_ops *ops, unsigned long flags, struct device *dev) mtk_clk_register_gate() argument
|
| H A D | clk-mt7622-aud.c | 56 .set_ofs = 0x0,
62 .set_ofs = 0x10,
68 .set_ofs = 0x14,
74 .set_ofs = 0x634,
|
| /kernel/linux/linux-6.6/drivers/clk/mediatek/ |
| H A D | clk-mt8183-ipu_conn.c | 15 .set_ofs = 0x4,
21 .set_ofs = 0x10,
27 .set_ofs = 0x18,
33 .set_ofs = 0x1c,
39 .set_ofs = 0x20,
|
| H A D | clk-mt8186-vdec.c | 16 .set_ofs = 0x0,
22 .set_ofs = 0x190,
28 .set_ofs = 0x200,
34 .set_ofs = 0x8,
|
| H A D | clk-mt8188-vdo1.c | 17 .set_ofs = 0x104,
23 .set_ofs = 0x114,
29 .set_ofs = 0x124,
35 .set_ofs = 0x134,
41 .set_ofs = 0x144,
|
| H A D | clk-mt8195-vdo1.c | 14 .set_ofs = 0x104,
20 .set_ofs = 0x124,
26 .set_ofs = 0x134,
32 .set_ofs = 0x144,
38 .set_ofs = 0x400,
|
| H A D | clk-gate.c | 20 int set_ofs; member
55 regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit)); in mtk_cg_set_bit()
157 struct regmap *regmap, int set_ofs, in mtk_clk_register_gate()
177 cg->set_ofs = set_ofs; in mtk_clk_register_gate()
233 gate->regs->set_ofs, in mtk_clk_register_gates()
155 mtk_clk_register_gate(struct device *dev, const char *name, const char *parent_name, struct regmap *regmap, int set_ofs, int clr_ofs, int sta_ofs, u8 bit, const struct clk_ops *ops, unsigned long flags) mtk_clk_register_gate() argument
|
| H A D | clk-mt8188-vdec.c | 15 .set_ofs = 0x0,
21 .set_ofs = 0x200,
27 .set_ofs = 0x8,
|
| H A D | clk-mt7986-eth.c | 18 .set_ofs = 0xe4,
34 .set_ofs = 0xe4,
50 .set_ofs = 0x30,
|
| H A D | clk-mt8195-vdec.c | 14 .set_ofs = 0x0,
20 .set_ofs = 0x200,
26 .set_ofs = 0x8,
|
| H A D | clk-mt8192-vdec.c | 16 .set_ofs = 0x0,
22 .set_ofs = 0x200,
28 .set_ofs = 0x8,
|
| H A D | clk-mt8188-infra_ao.c | 16 .set_ofs = 0x80,
22 .set_ofs = 0x88,
28 .set_ofs = 0xa4,
34 .set_ofs = 0xc0,
40 .set_ofs = 0xe0,
|
| H A D | clk-mt8195-infra_ao.c | 15 .set_ofs = 0x80,
21 .set_ofs = 0x88,
27 .set_ofs = 0xa4,
33 .set_ofs = 0xc0,
39 .set_ofs = 0xe0,
|
| H A D | clk-mt7622-aud.c | 32 .set_ofs = 0x0,
38 .set_ofs = 0x10,
44 .set_ofs = 0x14,
50 .set_ofs = 0x634,
|
| H A D | clk-mt2701-aud.c | 31 .set_ofs = 0x0,
37 .set_ofs = 0x10,
43 .set_ofs = 0x14,
49 .set_ofs = 0x634,
|
| H A D | clk-mt6795-vdecsys.c | 18 .set_ofs = 0x0000,
24 .set_ofs = 0x0008,
|
| H A D | clk-mt8173-vdecsys.c | 19 .set_ofs = 0x0000,
25 .set_ofs = 0x0008,
|
| H A D | clk-mt2712-mm.c | 16 .set_ofs = 0x104,
22 .set_ofs = 0x114,
28 .set_ofs = 0x224,
|
| H A D | clk-mt8192-aud.c | 16 .set_ofs = 0x0,
22 .set_ofs = 0x4,
28 .set_ofs = 0x8,
|
| H A D | clk-mt8188-wpe.c | 17 .set_ofs = 0x0,
23 .set_ofs = 0x58,
29 .set_ofs = 0x5c,
|
| H A D | clk-mt8188-vpp0.c | 15 .set_ofs = 0x24,
21 .set_ofs = 0x30,
27 .set_ofs = 0x3c,
|
| H A D | clk-mt8188-vdo0.c | 17 .set_ofs = 0x104,
23 .set_ofs = 0x114,
29 .set_ofs = 0x124,
|
| H A D | clk-mt7981-eth.c | 20 .set_ofs = 0xE4,
42 .set_ofs = 0xE4,
64 .set_ofs = 0x30,
|