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Searched refs:sdma_offsets (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v3_0.c74 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
366 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; in sdma_v3_0_ring_get_wptr()
393 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2); in sdma_v3_0_ring_set_wptr()
519 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_stop()
521 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v3_0_gfx_stop()
522 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_stop()
524 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in sdma_v3_0_gfx_stop()
578 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); in sdma_v3_0_ctx_switch_enable()
585 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], in sdma_v3_0_ctx_switch_enable()
587 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[ in sdma_v3_0_ctx_switch_enable()
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H A Dcik_sdma.c47 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
179 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2; in cik_sdma_ring_get_wptr()
193 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], in cik_sdma_ring_set_wptr()
314 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in cik_sdma_gfx_stop()
316 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in cik_sdma_gfx_stop()
317 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0); in cik_sdma_gfx_stop()
371 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); in cik_ctx_switch_enable()
376 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], in cik_ctx_switch_enable()
378 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], in cik_ctx_switch_enable()
386 WREG32(mmSDMA0_CNTL + sdma_offsets[ in cik_ctx_switch_enable()
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H A Dsdma_v2_4.c60 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
204 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; in sdma_v2_4_ring_get_wptr()
220 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2); in sdma_v2_4_ring_set_wptr()
345 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_stop()
347 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v2_4_gfx_stop()
348 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_stop()
350 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in sdma_v2_4_gfx_stop()
385 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in sdma_v2_4_enable()
390 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); in sdma_v2_4_enable()
416 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[ in sdma_v2_4_gfx_resume()
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H A Dsi_dma.c30 const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
51 return (RREG32(DMA_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2; in si_dma_ring_get_wptr()
59 WREG32(DMA_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc); in si_dma_ring_set_wptr()
122 rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); in si_dma_stop()
124 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_stop()
138 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); in si_dma_start()
139 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); in si_dma_start()
147 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_start()
150 WREG32(DMA_RB_RPTR + sdma_offsets[i], 0); in si_dma_start()
151 WREG32(DMA_RB_WPTR + sdma_offsets[ in si_dma_start()
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dcik_sdma.c47 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
183 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2; in cik_sdma_ring_get_wptr()
197 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], in cik_sdma_ring_set_wptr()
318 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in cik_sdma_gfx_stop()
320 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in cik_sdma_gfx_stop()
321 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0); in cik_sdma_gfx_stop()
375 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); in cik_ctx_switch_enable()
380 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], in cik_ctx_switch_enable()
382 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], in cik_ctx_switch_enable()
390 WREG32(mmSDMA0_CNTL + sdma_offsets[ in cik_ctx_switch_enable()
[all...]
H A Dsdma_v3_0.c74 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
372 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; in sdma_v3_0_ring_get_wptr()
399 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); in sdma_v3_0_ring_set_wptr()
525 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_stop()
527 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v3_0_gfx_stop()
528 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_stop()
530 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in sdma_v3_0_gfx_stop()
584 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); in sdma_v3_0_ctx_switch_enable()
591 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], in sdma_v3_0_ctx_switch_enable()
593 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[ in sdma_v3_0_ctx_switch_enable()
[all...]
H A Dsdma_v2_4.c60 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
210 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; in sdma_v2_4_ring_get_wptr()
226 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); in sdma_v2_4_ring_set_wptr()
351 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_stop()
353 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v2_4_gfx_stop()
354 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_stop()
356 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in sdma_v2_4_gfx_stop()
391 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in sdma_v2_4_enable()
396 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); in sdma_v2_4_enable()
424 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[ in sdma_v2_4_gfx_resume()
[all...]
H A Dsi_dma.c30 const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
51 return (RREG32(DMA_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2; in si_dma_ring_get_wptr()
59 WREG32(DMA_RB_WPTR + sdma_offsets[me], in si_dma_ring_set_wptr()
121 rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); in si_dma_stop()
123 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_stop()
140 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); in si_dma_start()
141 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); in si_dma_start()
149 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_start()
152 WREG32(DMA_RB_RPTR + sdma_offsets[i], 0); in si_dma_start()
153 WREG32(DMA_RB_WPTR + sdma_offsets[ in si_dma_start()
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