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Searched refs:sdma_cntl (Results 1 - 16 of 16) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dsi_dma.c592 u32 sdma_cntl; in si_dma_set_trap_irq_state() local
598 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
599 sdma_cntl &= ~TRAP_ENABLE; in si_dma_set_trap_irq_state()
600 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
603 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
604 sdma_cntl |= TRAP_ENABLE; in si_dma_set_trap_irq_state()
605 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
614 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
615 sdma_cntl &= ~TRAP_ENABLE; in si_dma_set_trap_irq_state()
616 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
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H A Dsdma_v2_4.c1009 u32 sdma_cntl; in sdma_v2_4_set_trap_irq_state() local
1015 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1016 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v2_4_set_trap_irq_state()
1017 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1020 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1021 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v2_4_set_trap_irq_state()
1022 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1031 sdma_cntl in sdma_v2_4_set_trap_irq_state()
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H A Dcik_sdma.c1113 u32 sdma_cntl; in cik_sdma_set_trap_irq_state() local
1119 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1120 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; in cik_sdma_set_trap_irq_state()
1121 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
1124 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1125 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; in cik_sdma_set_trap_irq_state()
1126 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
1135 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1136 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; in cik_sdma_set_trap_irq_state()
1137 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
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H A Dsdma_v3_0.c1343 u32 sdma_cntl; in sdma_v3_0_set_trap_irq_state() local
1349 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1350 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v3_0_set_trap_irq_state()
1351 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1354 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1355 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v3_0_set_trap_irq_state()
1356 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1365 sdma_cntl in sdma_v3_0_set_trap_irq_state()
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H A Dsdma_v5_2.c1403 u32 sdma_cntl; in sdma_v5_2_set_trap_irq_state() local
1407 sdma_cntl = RREG32(reg_offset); in sdma_v5_2_set_trap_irq_state()
1408 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v5_2_set_trap_irq_state()
1410 WREG32(reg_offset, sdma_cntl); in sdma_v5_2_set_trap_irq_state()
H A Dsdma_v5_0.c1433 u32 sdma_cntl; in sdma_v5_0_set_trap_irq_state() local
1440 sdma_cntl = RREG32(reg_offset); in sdma_v5_0_set_trap_irq_state()
1441 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v5_0_set_trap_irq_state()
1443 WREG32(reg_offset, sdma_cntl); in sdma_v5_0_set_trap_irq_state()
H A Dsdma_v4_0.c2058 u32 sdma_cntl; in sdma_v4_0_set_trap_irq_state() local
2060 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL); in sdma_v4_0_set_trap_irq_state()
2061 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v4_0_set_trap_irq_state()
2063 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl); in sdma_v4_0_set_trap_irq_state()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dsi_dma.c590 u32 sdma_cntl; in si_dma_set_trap_irq_state() local
596 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
597 sdma_cntl &= ~TRAP_ENABLE; in si_dma_set_trap_irq_state()
598 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
601 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
602 sdma_cntl |= TRAP_ENABLE; in si_dma_set_trap_irq_state()
603 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
612 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
613 sdma_cntl &= ~TRAP_ENABLE; in si_dma_set_trap_irq_state()
614 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
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H A Dsdma_v3_0.c1334 u32 sdma_cntl; in sdma_v3_0_set_trap_irq_state() local
1340 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1341 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v3_0_set_trap_irq_state()
1342 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1345 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1346 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v3_0_set_trap_irq_state()
1347 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1356 sdma_cntl in sdma_v3_0_set_trap_irq_state()
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H A Dsdma_v2_4.c1000 u32 sdma_cntl; in sdma_v2_4_set_trap_irq_state() local
1006 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1007 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v2_4_set_trap_irq_state()
1008 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1011 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1012 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v2_4_set_trap_irq_state()
1013 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1022 sdma_cntl in sdma_v2_4_set_trap_irq_state()
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H A Dcik_sdma.c1107 u32 sdma_cntl; in cik_sdma_set_trap_irq_state() local
1113 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1114 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; in cik_sdma_set_trap_irq_state()
1115 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
1118 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1119 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; in cik_sdma_set_trap_irq_state()
1120 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
1129 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1130 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; in cik_sdma_set_trap_irq_state()
1131 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
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H A Dsdma_v4_4_2.c1516 u32 sdma_cntl; in sdma_v4_4_2_set_trap_irq_state() local
1518 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); in sdma_v4_4_2_set_trap_irq_state()
1519 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE, in sdma_v4_4_2_set_trap_irq_state()
1521 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); in sdma_v4_4_2_set_trap_irq_state()
1612 u32 sdma_cntl; in sdma_v4_4_2_set_ecc_irq_state() local
1614 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); in sdma_v4_4_2_set_ecc_irq_state()
1617 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, in sdma_v4_4_2_set_ecc_irq_state()
1619 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); in sdma_v4_4_2_set_ecc_irq_state()
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H A Dsdma_v5_0.c1547 u32 sdma_cntl; in sdma_v5_0_set_trap_irq_state() local
1554 sdma_cntl = RREG32(reg_offset); in sdma_v5_0_set_trap_irq_state()
1555 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v5_0_set_trap_irq_state()
1557 WREG32(reg_offset, sdma_cntl); in sdma_v5_0_set_trap_irq_state()
H A Dsdma_v5_2.c1398 u32 sdma_cntl; in sdma_v5_2_set_trap_irq_state() local
1402 sdma_cntl = RREG32(reg_offset); in sdma_v5_2_set_trap_irq_state()
1403 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v5_2_set_trap_irq_state()
1405 WREG32(reg_offset, sdma_cntl); in sdma_v5_2_set_trap_irq_state()
H A Dsdma_v6_0.c1454 u32 sdma_cntl; in sdma_v6_0_set_trap_irq_state() local
1459 sdma_cntl = RREG32(reg_offset); in sdma_v6_0_set_trap_irq_state()
1460 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v6_0_set_trap_irq_state()
1462 WREG32(reg_offset, sdma_cntl); in sdma_v6_0_set_trap_irq_state()
H A Dsdma_v4_0.c2016 u32 sdma_cntl; in sdma_v4_0_set_trap_irq_state() local
2018 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL); in sdma_v4_0_set_trap_irq_state()
2019 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v4_0_set_trap_irq_state()
2021 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl); in sdma_v4_0_set_trap_irq_state()

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