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Searched refs:reg_off (Results 1 - 25 of 129) sorted by relevance

123456

/kernel/linux/linux-6.6/tools/lib/bpf/
H A Dusdt.c208 short reg_off; member
1244 #define reg_off(reg64, reg32) offsetof(struct pt_regs, reg64) in calc_pt_regs_off() macro
1246 #define reg_off(reg64, reg32) offsetof(struct pt_regs, reg32) in calc_pt_regs_off()
1248 { {"rip", "eip", "", ""}, reg_off(rip, eip) }, in calc_pt_regs_off()
1249 { {"rax", "eax", "ax", "al"}, reg_off(rax, eax) }, in calc_pt_regs_off()
1250 { {"rbx", "ebx", "bx", "bl"}, reg_off(rbx, ebx) }, in calc_pt_regs_off()
1251 { {"rcx", "ecx", "cx", "cl"}, reg_off(rcx, ecx) }, in calc_pt_regs_off()
1252 { {"rdx", "edx", "dx", "dl"}, reg_off(rdx, edx) }, in calc_pt_regs_off()
1253 { {"rsi", "esi", "si", "sil"}, reg_off(rsi, esi) }, in calc_pt_regs_off()
1254 { {"rdi", "edi", "di", "dil"}, reg_off(rd in calc_pt_regs_off()
1257 #undef reg_off calc_pt_regs_off() macro
1285 int len, reg_off; parse_usdt_arg() local
1386 int len, reg_off; parse_usdt_arg() local
1480 int len, reg_off; parse_usdt_arg() local
1551 int len, reg_off; parse_usdt_arg() local
[all...]
/kernel/linux/linux-5.10/drivers/mmc/host/
H A Dcavium.h37 #define MIO_EMM_CFG(x) (0x00 + x->reg_off)
38 #define MIO_EMM_SWITCH(x) (0x48 + x->reg_off)
39 #define MIO_EMM_DMA(x) (0x50 + x->reg_off)
40 #define MIO_EMM_CMD(x) (0x58 + x->reg_off)
41 #define MIO_EMM_RSP_STS(x) (0x60 + x->reg_off)
42 #define MIO_EMM_RSP_LO(x) (0x68 + x->reg_off)
43 #define MIO_EMM_RSP_HI(x) (0x70 + x->reg_off)
44 #define MIO_EMM_INT(x) (0x78 + x->reg_off)
45 #define MIO_EMM_INT_EN(x) (0x80 + x->reg_off)
46 #define MIO_EMM_WDOG(x) (0x88 + x->reg_off)
59 int reg_off; global() member
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/kernel/linux/linux-6.6/drivers/mmc/host/
H A Dcavium.h37 #define MIO_EMM_CFG(x) (0x00 + x->reg_off)
38 #define MIO_EMM_SWITCH(x) (0x48 + x->reg_off)
39 #define MIO_EMM_DMA(x) (0x50 + x->reg_off)
40 #define MIO_EMM_CMD(x) (0x58 + x->reg_off)
41 #define MIO_EMM_RSP_STS(x) (0x60 + x->reg_off)
42 #define MIO_EMM_RSP_LO(x) (0x68 + x->reg_off)
43 #define MIO_EMM_RSP_HI(x) (0x70 + x->reg_off)
44 #define MIO_EMM_INT(x) (0x78 + x->reg_off)
45 #define MIO_EMM_INT_EN(x) (0x80 + x->reg_off)
46 #define MIO_EMM_WDOG(x) (0x88 + x->reg_off)
59 int reg_off; global() member
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/kernel/linux/linux-6.6/tools/testing/selftests/kvm/riscv/
H A Dget-reg-list.c117 /* reg_off is the offset into struct kvm_riscv_config */ in config_id_to_str()
118 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CONFIG); in config_id_to_str() local
120 switch (reg_off) { in config_id_to_str()
141 return strdup_printf("KVM_REG_RISCV_CONFIG_REG(%lld) /* UNKNOWN */", reg_off); in config_id_to_str()
146 /* reg_off is the offset into struct kvm_riscv_core */ in core_id_to_str()
147 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CORE); in core_id_to_str() local
149 switch (reg_off) { in core_id_to_str()
162 reg_off - KVM_REG_RISCV_CORE_REG(regs.t0)); in core_id_to_str()
165 reg_off - KVM_REG_RISCV_CORE_REG(regs.s0)); in core_id_to_str()
168 reg_off in core_id_to_str()
188 general_csr_id_to_str(__u64 reg_off) general_csr_id_to_str() argument
218 aia_csr_id_to_str(__u64 reg_off) aia_csr_id_to_str() argument
244 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR); csr_id_to_str() local
263 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_TIMER); timer_id_to_str() local
283 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_F); fp_f_id_to_str() local
300 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_D); fp_d_id_to_str() local
317 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_ISA_EXT); isa_ext_id_to_str() local
356 sbi_ext_single_id_to_str(__u64 reg_off) sbi_ext_single_id_to_str() argument
382 sbi_ext_multi_id_to_str(__u64 reg_subtype, __u64 reg_off) sbi_ext_multi_id_to_str() argument
404 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_EXT); sbi_ext_id_to_str() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_vbif.c59 u32 reg_off; in dpu_hw_set_mem_type() local
74 reg_off = VBIF_OUT_AXI_AMEMTYPE_CONF1; in dpu_hw_set_mem_type()
76 reg_off = VBIF_OUT_AXI_AMEMTYPE_CONF0; in dpu_hw_set_mem_type()
79 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_mem_type()
82 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type()
90 u32 reg_off; in dpu_hw_set_limit_conf() local
94 reg_off = VBIF_IN_RD_LIM_CONF0; in dpu_hw_set_limit_conf()
96 reg_off = VBIF_IN_WR_LIM_CONF0; in dpu_hw_set_limit_conf()
98 reg_off += (xin_id / 4) * 4; in dpu_hw_set_limit_conf()
100 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_limit_conf()
111 u32 reg_off; dpu_hw_get_limit_conf() local
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/kernel/linux/linux-6.6/drivers/pinctrl/sunplus/
H A Dsppctl.c111 static inline u32 sppctl_get_reg_and_bit_offset(unsigned int offset, u32 *reg_off) in sppctl_get_reg_and_bit_offset() argument
116 *reg_off = (offset / 32) * 4; in sppctl_get_reg_and_bit_offset()
122 static inline u32 sppctl_get_moon_reg_and_bit_offset(unsigned int offset, u32 *reg_off) in sppctl_get_moon_reg_and_bit_offset() argument
132 *reg_off = (offset / 16) * 4; in sppctl_get_moon_reg_and_bit_offset()
138 static inline u32 sppctl_prep_moon_reg_and_offset(unsigned int offset, u32 *reg_off, int val) in sppctl_prep_moon_reg_and_offset() argument
142 bit_off = sppctl_get_moon_reg_and_bit_offset(offset, reg_off); in sppctl_prep_moon_reg_and_offset()
226 static void sppctl_gmx_set(struct sppctl_pdata *pctl, u8 reg_off, u8 bit_off, u8 bit_sz, in sppctl_gmx_set() argument
239 writel(reg, pctl->moon1_base + reg_off * 4); in sppctl_gmx_set()
263 u32 reg_off, bit_off, reg; in sppctl_first_get() local
265 bit_off = sppctl_get_reg_and_bit_offset(offset, &reg_off); in sppctl_first_get()
298 u32 reg_off, bit_off, reg; sppctl_master_get() local
309 u32 reg_off, bit_off, reg; sppctl_first_master_set() local
345 u32 reg_off, reg; sppctl_gpio_input_inv_set() local
354 u32 reg_off, reg; sppctl_gpio_output_inv_set() local
363 u32 reg_off, bit_off, reg; sppctl_gpio_output_od_get() local
375 u32 reg_off, reg; sppctl_gpio_output_od_set() local
384 u32 reg_off, bit_off, reg; sppctl_gpio_get_direction() local
395 u32 reg_off, bit_off, reg; sppctl_gpio_inv_get() local
416 u32 reg_off, reg; sppctl_gpio_direction_input() local
432 u32 reg_off, reg; sppctl_gpio_direction_output() local
455 u32 reg_off, bit_off, reg; sppctl_gpio_get() local
466 u32 reg_off, reg; sppctl_gpio_set() local
477 u32 reg_off, reg; sppctl_gpio_set_config() local
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/kernel/linux/linux-5.10/drivers/pinctrl/
H A Dpinctrl-digicolor.c129 int bit_off, reg_off; in dc_set_mux() local
132 dc_client_sel(group, &reg_off, &bit_off); in dc_set_mux()
134 reg = readb_relaxed(pmap->regs + reg_off); in dc_set_mux()
137 writeb_relaxed(reg, pmap->regs + reg_off); in dc_set_mux()
147 int bit_off, reg_off; in dc_pmx_request_gpio() local
150 dc_client_sel(offset, &reg_off, &bit_off); in dc_pmx_request_gpio()
152 reg = readb_relaxed(pmap->regs + reg_off); in dc_pmx_request_gpio()
170 int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION); in dc_gpio_direction_input() local
176 drive = readb_relaxed(pmap->regs + reg_off); in dc_gpio_direction_input()
178 writeb_relaxed(drive, pmap->regs + reg_off); in dc_gpio_direction_input()
190 int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION); dc_gpio_direction_output() local
209 int reg_off = GP_INPUT(gpio/PINS_PER_COLLECTION); dc_gpio_get() local
221 int reg_off = GP_OUTPUT0(gpio/PINS_PER_COLLECTION); dc_gpio_set() local
[all...]
/kernel/linux/linux-6.6/drivers/pinctrl/
H A Dpinctrl-digicolor.c130 int bit_off, reg_off; in dc_set_mux() local
133 dc_client_sel(group, &reg_off, &bit_off); in dc_set_mux()
135 reg = readb_relaxed(pmap->regs + reg_off); in dc_set_mux()
138 writeb_relaxed(reg, pmap->regs + reg_off); in dc_set_mux()
148 int bit_off, reg_off; in dc_pmx_request_gpio() local
151 dc_client_sel(offset, &reg_off, &bit_off); in dc_pmx_request_gpio()
153 reg = readb_relaxed(pmap->regs + reg_off); in dc_pmx_request_gpio()
171 int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION); in dc_gpio_direction_input() local
177 drive = readb_relaxed(pmap->regs + reg_off); in dc_gpio_direction_input()
179 writeb_relaxed(drive, pmap->regs + reg_off); in dc_gpio_direction_input()
191 int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION); dc_gpio_direction_output() local
210 int reg_off = GP_INPUT(gpio/PINS_PER_COLLECTION); dc_gpio_get() local
222 int reg_off = GP_OUTPUT0(gpio/PINS_PER_COLLECTION); dc_gpio_set() local
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/kernel/linux/linux-6.6/drivers/clk/meson/
H A Da1-pll.c22 .reg_off = ANACTRL_FIXPLL_CTRL0,
27 .reg_off = ANACTRL_FIXPLL_CTRL0,
32 .reg_off = ANACTRL_FIXPLL_CTRL0,
37 .reg_off = ANACTRL_FIXPLL_CTRL1,
42 .reg_off = ANACTRL_FIXPLL_STS,
47 .reg_off = ANACTRL_FIXPLL_CTRL0,
93 .reg_off = ANACTRL_HIFIPLL_CTRL0,
98 .reg_off = ANACTRL_HIFIPLL_CTRL0,
103 .reg_off = ANACTRL_HIFIPLL_CTRL0,
108 .reg_off
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H A Dg12a-aoclk.c124 .reg_off = AO_RTC_ALT_CLK_CNTL0,
129 .reg_off = AO_RTC_ALT_CLK_CNTL0,
134 .reg_off = AO_RTC_ALT_CLK_CNTL1,
139 .reg_off = AO_RTC_ALT_CLK_CNTL1,
144 .reg_off = AO_RTC_ALT_CLK_CNTL0,
215 .reg_off = AO_CEC_CLK_CNTL_REG0,
220 .reg_off = AO_CEC_CLK_CNTL_REG0,
225 .reg_off = AO_CEC_CLK_CNTL_REG1,
230 .reg_off = AO_CEC_CLK_CNTL_REG1,
235 .reg_off
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H A Daxg.c31 .reg_off = HHI_MPLL_CNTL,
36 .reg_off = HHI_MPLL_CNTL,
41 .reg_off = HHI_MPLL_CNTL,
46 .reg_off = HHI_MPLL_CNTL2,
51 .reg_off = HHI_MPLL_CNTL,
56 .reg_off = HHI_MPLL_CNTL,
95 .reg_off = HHI_SYS_PLL_CNTL,
100 .reg_off = HHI_SYS_PLL_CNTL,
105 .reg_off = HHI_SYS_PLL_CNTL,
110 .reg_off
[all...]
H A Dmeson8-ddr.c28 .reg_off = AM_DDR_PLL_CNTL,
33 .reg_off = AM_DDR_PLL_CNTL,
38 .reg_off = AM_DDR_PLL_CNTL,
43 .reg_off = AM_DDR_PLL_CNTL,
48 .reg_off = AM_DDR_PLL_CNTL,
H A Dgxbb.c91 .reg_off = HHI_MPLL_CNTL,
96 .reg_off = HHI_MPLL_CNTL,
101 .reg_off = HHI_MPLL_CNTL,
106 .reg_off = HHI_MPLL_CNTL2,
111 .reg_off = HHI_MPLL_CNTL,
116 .reg_off = HHI_MPLL_CNTL,
168 .reg_off = HHI_HDMI_PLL_CNTL,
173 .reg_off = HHI_HDMI_PLL_CNTL,
178 .reg_off = HHI_HDMI_PLL_CNTL,
183 .reg_off
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_vbif.c59 u32 reg_off; in dpu_hw_set_mem_type() local
74 reg_off = VBIF_OUT_AXI_AMEMTYPE_CONF1; in dpu_hw_set_mem_type()
76 reg_off = VBIF_OUT_AXI_AMEMTYPE_CONF0; in dpu_hw_set_mem_type()
79 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_mem_type()
82 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type()
90 u32 reg_off; in dpu_hw_set_limit_conf() local
94 reg_off = VBIF_IN_RD_LIM_CONF0; in dpu_hw_set_limit_conf()
96 reg_off = VBIF_IN_WR_LIM_CONF0; in dpu_hw_set_limit_conf()
98 reg_off += (xin_id / 4) * 4; in dpu_hw_set_limit_conf()
100 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_limit_conf()
111 u32 reg_off; dpu_hw_get_limit_conf() local
[all...]
H A Ddpu_hw_catalog.c133 .reg_off = 0x2AC, .bit_off = 0},
135 .reg_off = 0x2B4, .bit_off = 0},
137 .reg_off = 0x2BC, .bit_off = 0},
139 .reg_off = 0x2C4, .bit_off = 0},
141 .reg_off = 0x2AC, .bit_off = 8},
143 .reg_off = 0x2B4, .bit_off = 8},
145 .reg_off = 0x2BC, .bit_off = 8},
147 .reg_off = 0x2C4, .bit_off = 8},
158 .reg_off = 0x2AC, .bit_off = 0},
160 .reg_off
[all...]
/kernel/linux/linux-5.10/drivers/clk/meson/
H A Daxg.c28 .reg_off = HHI_MPLL_CNTL,
33 .reg_off = HHI_MPLL_CNTL,
38 .reg_off = HHI_MPLL_CNTL,
43 .reg_off = HHI_MPLL_CNTL2,
48 .reg_off = HHI_MPLL_CNTL,
53 .reg_off = HHI_MPLL_CNTL,
92 .reg_off = HHI_SYS_PLL_CNTL,
97 .reg_off = HHI_SYS_PLL_CNTL,
102 .reg_off = HHI_SYS_PLL_CNTL,
107 .reg_off
[all...]
H A Dg12a-aoclk.c121 .reg_off = AO_RTC_ALT_CLK_CNTL0,
126 .reg_off = AO_RTC_ALT_CLK_CNTL0,
131 .reg_off = AO_RTC_ALT_CLK_CNTL1,
136 .reg_off = AO_RTC_ALT_CLK_CNTL1,
141 .reg_off = AO_RTC_ALT_CLK_CNTL0,
212 .reg_off = AO_CEC_CLK_CNTL_REG0,
217 .reg_off = AO_CEC_CLK_CNTL_REG0,
222 .reg_off = AO_CEC_CLK_CNTL_REG1,
227 .reg_off = AO_CEC_CLK_CNTL_REG1,
232 .reg_off
[all...]
H A Dmeson8-ddr.c28 .reg_off = AM_DDR_PLL_CNTL,
33 .reg_off = AM_DDR_PLL_CNTL,
38 .reg_off = AM_DDR_PLL_CNTL,
43 .reg_off = AM_DDR_PLL_CNTL,
48 .reg_off = AM_DDR_PLL_CNTL,
H A Dgxbb.c88 .reg_off = HHI_MPLL_CNTL,
93 .reg_off = HHI_MPLL_CNTL,
98 .reg_off = HHI_MPLL_CNTL,
103 .reg_off = HHI_MPLL_CNTL2,
108 .reg_off = HHI_MPLL_CNTL,
113 .reg_off = HHI_MPLL_CNTL,
165 .reg_off = HHI_HDMI_PLL_CNTL,
170 .reg_off = HHI_HDMI_PLL_CNTL,
175 .reg_off = HHI_HDMI_PLL_CNTL,
180 .reg_off
[all...]
/kernel/linux/linux-5.10/drivers/irqchip/
H A Dirq-davinci-aintc.c82 unsigned int irq_off, reg_off, prio, shift; in davinci_aintc_init() local
125 for (reg_off = DAVINCI_AINTC_IRQ_INTPRI0_REG; in davinci_aintc_init()
126 reg_off <= DAVINCI_AINTC_IRQ_INTPRI7_REG; reg_off += 4) { in davinci_aintc_init()
129 davinci_aintc_writel(prio, reg_off); in davinci_aintc_init()
156 for (irq_off = 0, reg_off = 0; in davinci_aintc_init()
158 irq_off += 32, reg_off += 0x04) in davinci_aintc_init()
159 davinci_aintc_setup_gc(davinci_aintc_base + reg_off, in davinci_aintc_init()
/kernel/linux/linux-6.6/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_main.h305 #define octep_write_csr(octep_dev, reg_off, value) \
306 writel(value, (octep_dev)->mmio[0].hw_addr + (reg_off))
308 #define octep_write_csr64(octep_dev, reg_off, val64) \
309 writeq(val64, (octep_dev)->mmio[0].hw_addr + (reg_off))
311 #define octep_read_csr(octep_dev, reg_off) \
312 readl((octep_dev)->mmio[0].hw_addr + (reg_off))
314 #define octep_read_csr64(octep_dev, reg_off) \
315 readq((octep_dev)->mmio[0].hw_addr + (reg_off))
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_3_0_msm8998.h29 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
32 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
33 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
36 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },
37 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
38 [DPU_CLK_CTRL_CURSOR1] = { .reg_off
[all...]
H A Ddpu_9_0_sm8550.h27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 },
31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 },
32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 },
33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 },
34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 },
35 [DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 },
36 [DPU_CLK_CTRL_DMA5] = { .reg_off
[all...]
/kernel/linux/linux-6.6/sound/soc/tegra/
H A Dtegra210_mbdrc.c787 u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE; in tegra210_mbdrc_hw_params() local
790 reg_off + TEGRA210_MBDRC_CFG_RAM_CTRL, in tegra210_mbdrc_hw_params()
791 reg_off + TEGRA210_MBDRC_CFG_RAM_DATA, in tegra210_mbdrc_hw_params()
849 u32 reg_off = i * TEGRA210_MBDRC_FILTER_PARAM_STRIDE; in tegra210_mbdrc_component_init() local
852 reg_off + TEGRA210_MBDRC_IIR_CFG, in tegra210_mbdrc_component_init()
858 reg_off + TEGRA210_MBDRC_IN_ATTACK, in tegra210_mbdrc_component_init()
864 reg_off + TEGRA210_MBDRC_IN_RELEASE, in tegra210_mbdrc_component_init()
870 reg_off + TEGRA210_MBDRC_FAST_ATTACK, in tegra210_mbdrc_component_init()
889 reg_off + TEGRA210_MBDRC_IN_THRESHOLD, in tegra210_mbdrc_component_init()
906 reg_off in tegra210_mbdrc_component_init()
[all...]
/kernel/linux/linux-5.10/drivers/pinctrl/spear/
H A Dpinctrl-plgpio.c83 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in is_plgpio_set() local
84 u32 val = readl_relaxed(reg_off); in is_plgpio_set()
92 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in plgpio_reg_set() local
93 u32 val = readl_relaxed(reg_off); in plgpio_reg_set()
95 writel_relaxed(val | (1 << offset), reg_off); in plgpio_reg_set()
101 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in plgpio_reg_reset() local
102 u32 val = readl_relaxed(reg_off); in plgpio_reg_reset()
104 writel_relaxed(val & ~(1 << offset), reg_off); in plgpio_reg_reset()
323 void __iomem *reg_off; in plgpio_irq_set_type() local
340 reg_off in plgpio_irq_set_type()
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