| /kernel/linux/linux-6.6/drivers/clk/nuvoton/ |
| H A D | clk-ma35d1-pll.c | 99 static unsigned long ma35d1_calc_pll_freq(u8 mode, u32 *reg_ctl, unsigned long parent_rate) in ma35d1_calc_pll_freq() argument
104 if (reg_ctl[1] & PLL_CTL1_BP) in ma35d1_calc_pll_freq()
107 n = FIELD_GET(PLL_CTL0_FBDIV, reg_ctl[0]); in ma35d1_calc_pll_freq()
108 m = FIELD_GET(PLL_CTL0_INDIV, reg_ctl[0]); in ma35d1_calc_pll_freq()
109 p = FIELD_GET(PLL_CTL1_OUTDIV, reg_ctl[1]); in ma35d1_calc_pll_freq()
115 x = FIELD_GET(PLL_CTL1_FRAC, reg_ctl[1]); in ma35d1_calc_pll_freq()
124 unsigned long parent_rate, u32 *reg_ctl, in ma35d1_pll_find_closest()
169 reg_ctl[0] = FIELD_PREP(PLL_CTL0_INDIV, m) | in ma35d1_pll_find_closest()
171 reg_ctl[1] = FIELD_PREP(PLL_CTL1_OUTDIV, p); in ma35d1_pll_find_closest()
189 u32 reg_ctl[ in ma35d1_clk_pll_set_rate() local
123 ma35d1_pll_find_closest(struct ma35d1_clk_pll *pll, unsigned long rate, unsigned long parent_rate, u32 *reg_ctl, unsigned long *freq) ma35d1_pll_find_closest() argument
224 u32 reg_ctl[3]; ma35d1_clk_pll_recalc_rate() local
251 u32 reg_ctl[3] = { 0 }; ma35d1_clk_pll_round_rate() local
[all...] |
| /kernel/linux/linux-5.10/drivers/clk/baikal-t1/ |
| H A D | ccu-div.c | 93 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_var_update_clkdiv()
103 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_var_update_clkdiv()
124 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_var_enable()
132 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_var_enable()
147 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_gate_enable()
160 regmap_update_bits(div->sys_regs, div->reg_ctl, CCU_DIV_CTL_EN, 0); in ccu_div_gate_disable()
169 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_gate_is_enabled()
180 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_buf_enable()
193 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_buf_disable()
203 regmap_read(div->sys_regs, div->reg_ctl, in ccu_div_buf_is_enabled()
[all...] |
| H A D | ccu-pll.c | 97 regmap_update_bits(pll->sys_regs, pll->reg_ctl, in ccu_pll_reset()
100 return regmap_read_poll_timeout_atomic(pll->sys_regs, pll->reg_ctl, val, in ccu_pll_reset()
117 regmap_read(pll->sys_regs, pll->reg_ctl, &val); in ccu_pll_enable()
122 regmap_write(pll->sys_regs, pll->reg_ctl, val | CCU_PLL_CTL_EN); in ccu_pll_enable()
138 regmap_update_bits(pll->sys_regs, pll->reg_ctl, CCU_PLL_CTL_EN, 0); in ccu_pll_disable()
147 regmap_read(pll->sys_regs, pll->reg_ctl, &val); in ccu_pll_is_enabled()
159 regmap_read(pll->sys_regs, pll->reg_ctl, &val); in ccu_pll_recalc_rate()
263 regmap_update_bits(pll->sys_regs, pll->reg_ctl, mask, val); in ccu_pll_set_rate_reset()
297 regmap_update_bits(pll->sys_regs, pll->reg_ctl, mask, val); in ccu_pll_set_rate_norst()
376 regmap_update_bits(pll->sys_regs, pll->reg_ctl in ccu_pll_dbgfs_bit_set()
[all...] |
| H A D | ccu-pll.h | 40 * @reg_ctl: PLL control register base.
48 unsigned int reg_ctl; member
|
| H A D | ccu-div.h | 86 * @reg_ctl: Divider control register base address.
97 unsigned int reg_ctl; member
|
| /kernel/linux/linux-6.6/drivers/clk/baikal-t1/ |
| H A D | ccu-div.c | 92 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_var_update_clkdiv()
102 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_var_update_clkdiv()
123 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_var_enable()
131 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_var_enable()
146 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_gate_enable()
159 regmap_update_bits(div->sys_regs, div->reg_ctl, CCU_DIV_CTL_EN, 0); in ccu_div_gate_disable()
168 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_gate_is_enabled()
179 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_buf_enable()
192 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_buf_disable()
202 regmap_read(div->sys_regs, div->reg_ctl, in ccu_div_buf_is_enabled()
[all...] |
| H A D | ccu-pll.c | 97 regmap_update_bits(pll->sys_regs, pll->reg_ctl, in ccu_pll_reset()
100 return regmap_read_poll_timeout_atomic(pll->sys_regs, pll->reg_ctl, val, in ccu_pll_reset()
117 regmap_read(pll->sys_regs, pll->reg_ctl, &val); in ccu_pll_enable()
122 regmap_write(pll->sys_regs, pll->reg_ctl, val | CCU_PLL_CTL_EN); in ccu_pll_enable()
138 regmap_update_bits(pll->sys_regs, pll->reg_ctl, CCU_PLL_CTL_EN, 0); in ccu_pll_disable()
147 regmap_read(pll->sys_regs, pll->reg_ctl, &val); in ccu_pll_is_enabled()
159 regmap_read(pll->sys_regs, pll->reg_ctl, &val); in ccu_pll_recalc_rate()
263 regmap_update_bits(pll->sys_regs, pll->reg_ctl, mask, val); in ccu_pll_set_rate_reset()
297 regmap_update_bits(pll->sys_regs, pll->reg_ctl, mask, val); in ccu_pll_set_rate_norst()
376 regmap_update_bits(pll->sys_regs, pll->reg_ctl in ccu_pll_dbgfs_bit_set()
[all...] |
| H A D | ccu-pll.h | 48 * @reg_ctl: PLL control register base.
56 unsigned int reg_ctl; member
|
| H A D | ccu-div.h | 89 * @reg_ctl: Divider control register base address.
100 unsigned int reg_ctl; member
|