Lines Matching refs:reg_ctl
99 static unsigned long ma35d1_calc_pll_freq(u8 mode, u32 *reg_ctl, unsigned long parent_rate)
104 if (reg_ctl[1] & PLL_CTL1_BP)
107 n = FIELD_GET(PLL_CTL0_FBDIV, reg_ctl[0]);
108 m = FIELD_GET(PLL_CTL0_INDIV, reg_ctl[0]);
109 p = FIELD_GET(PLL_CTL1_OUTDIV, reg_ctl[1]);
115 x = FIELD_GET(PLL_CTL1_FRAC, reg_ctl[1]);
124 unsigned long parent_rate, u32 *reg_ctl,
169 reg_ctl[0] = FIELD_PREP(PLL_CTL0_INDIV, m) |
171 reg_ctl[1] = FIELD_PREP(PLL_CTL1_OUTDIV, p);
189 u32 reg_ctl[3] = { 0 };
196 ret = ma35d1_pll_find_closest(pll, rate, parent_rate, reg_ctl, &pll_freq);
202 reg_ctl[0] |= FIELD_PREP(PLL_CTL0_MODE, PLL_MODE_INT);
205 reg_ctl[0] |= FIELD_PREP(PLL_CTL0_MODE, PLL_MODE_FRAC);
208 reg_ctl[0] |= FIELD_PREP(PLL_CTL0_MODE, PLL_MODE_SS) |
210 reg_ctl[2] = FIELD_PREP(PLL_CTL2_SLOPE, PLL_SLOPE);
213 reg_ctl[1] |= PLL_CTL1_PD;
215 writel_relaxed(reg_ctl[0], pll->ctl0_base);
216 writel_relaxed(reg_ctl[1], pll->ctl1_base);
217 writel_relaxed(reg_ctl[2], pll->ctl2_base);
224 u32 reg_ctl[3];
232 reg_ctl[0] = readl_relaxed(pll->ctl0_base);
233 pll_freq = ma35d1_calc_smic_pll_freq(reg_ctl[0], parent_rate);
239 reg_ctl[0] = readl_relaxed(pll->ctl0_base);
240 reg_ctl[1] = readl_relaxed(pll->ctl1_base);
241 pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, parent_rate);
251 u32 reg_ctl[3] = { 0 };
258 ret = ma35d1_pll_find_closest(pll, rate, *parent_rate, reg_ctl, &pll_freq);
264 reg_ctl[0] = readl_relaxed(pll->ctl0_base);
265 pll_freq = ma35d1_calc_smic_pll_freq(reg_ctl[0], *parent_rate);
271 reg_ctl[0] = readl_relaxed(pll->ctl0_base);
272 reg_ctl[1] = readl_relaxed(pll->ctl1_base);
273 pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, *parent_rate);