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Searched refs:rb_cntl (Results 1 - 24 of 24) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Dni_dma.c159 u32 rb_cntl; in cayman_dma_stop() local
166 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop()
167 rb_cntl &= ~DMA_RB_ENABLE; in cayman_dma_stop()
168 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
171 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_dma_stop()
172 rb_cntl &= ~DMA_RB_ENABLE; in cayman_dma_stop()
173 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
190 u32 rb_cntl, dma_cntl, ib_cntl; in cayman_dma_resume() local
211 rb_cntl = rb_bufsz << 1; in cayman_dma_resume()
213 rb_cntl | in cayman_dma_resume()
[all...]
H A Dr600_dma.c101 u32 rb_cntl = RREG32(DMA_RB_CNTL); in r600_dma_stop() local
106 rb_cntl &= ~DMA_RB_ENABLE; in r600_dma_stop()
107 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_stop()
123 u32 rb_cntl, dma_cntl, ib_cntl; in r600_dma_resume() local
132 rb_cntl = rb_bufsz << 1; in r600_dma_resume()
134 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; in r600_dma_resume()
136 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_resume()
149 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; in r600_dma_resume()
170 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); in r600_dma_resume()
H A Dcik_sdma.c252 u32 rb_cntl, reg_offset; in cik_sdma_gfx_stop() local
264 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); in cik_sdma_gfx_stop()
265 rb_cntl &= ~SDMA_RB_ENABLE; in cik_sdma_gfx_stop()
266 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_stop()
368 u32 rb_cntl, ib_cntl; in cik_sdma_gfx_resume() local
389 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
391 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; in cik_sdma_gfx_resume()
393 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_resume()
406 rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE; in cik_sdma_gfx_resume()
415 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABL in cik_sdma_gfx_resume()
[all...]
H A Dni.c1689 uint32_t rb_cntl; in cayman_cp_resume() local
1694 rb_cntl = order_base_2(ring->ring_size / 8); in cayman_cp_resume()
1695 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8; in cayman_cp_resume()
1697 rb_cntl |= BUF_SWAP_32BIT; in cayman_cp_resume()
1699 WREG32(cp_rb_cntl[i], rb_cntl); in cayman_cp_resume()
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Dni_dma.c158 u32 rb_cntl; in cayman_dma_stop() local
165 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop()
166 rb_cntl &= ~DMA_RB_ENABLE; in cayman_dma_stop()
167 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
170 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_dma_stop()
171 rb_cntl &= ~DMA_RB_ENABLE; in cayman_dma_stop()
172 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
189 u32 rb_cntl, dma_cntl, ib_cntl; in cayman_dma_resume() local
210 rb_cntl = rb_bufsz << 1; in cayman_dma_resume()
212 rb_cntl | in cayman_dma_resume()
[all...]
H A Dr600_dma.c100 u32 rb_cntl = RREG32(DMA_RB_CNTL); in r600_dma_stop() local
105 rb_cntl &= ~DMA_RB_ENABLE; in r600_dma_stop()
106 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_stop()
122 u32 rb_cntl, dma_cntl, ib_cntl; in r600_dma_resume() local
131 rb_cntl = rb_bufsz << 1; in r600_dma_resume()
133 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; in r600_dma_resume()
135 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_resume()
148 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; in r600_dma_resume()
169 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); in r600_dma_resume()
H A Dcik_sdma.c251 u32 rb_cntl, reg_offset; in cik_sdma_gfx_stop() local
263 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); in cik_sdma_gfx_stop()
264 rb_cntl &= ~SDMA_RB_ENABLE; in cik_sdma_gfx_stop()
265 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_stop()
367 u32 rb_cntl, ib_cntl; in cik_sdma_gfx_resume() local
388 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
390 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; in cik_sdma_gfx_resume()
392 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_resume()
405 rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE; in cik_sdma_gfx_resume()
414 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABL in cik_sdma_gfx_resume()
[all...]
H A Dni.c1676 uint32_t rb_cntl; in cayman_cp_resume() local
1681 rb_cntl = order_base_2(ring->ring_size / 8); in cayman_cp_resume()
1682 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8; in cayman_cp_resume()
1684 rb_cntl |= BUF_SWAP_32BIT; in cayman_cp_resume()
1686 WREG32(cp_rb_cntl[i], rb_cntl); in cayman_cp_resume()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v4_4_2.c429 u32 rb_cntl, ib_cntl; in sdma_v4_4_2_inst_gfx_stop() local
440 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); in sdma_v4_4_2_inst_gfx_stop()
441 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v4_4_2_inst_gfx_stop()
442 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); in sdma_v4_4_2_inst_gfx_stop()
475 u32 rb_cntl, ib_cntl; in sdma_v4_4_2_inst_page_stop() local
488 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); in sdma_v4_4_2_inst_page_stop()
489 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, in sdma_v4_4_2_inst_page_stop()
491 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); in sdma_v4_4_2_inst_page_stop()
594 sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) sdma_v4_4_2_rb_cntl() argument
621 u32 rb_cntl, ib_cntl, wptr_poll_cntl; sdma_v4_4_2_gfx_resume() local
709 u32 rb_cntl, ib_cntl, wptr_poll_cntl; sdma_v4_4_2_page_resume() local
[all...]
H A Dsdma_v4_0.c875 u32 rb_cntl, ib_cntl; in sdma_v4_0_gfx_enable() local
881 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); in sdma_v4_0_gfx_enable()
882 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, enable ? 1 : 0); in sdma_v4_0_gfx_enable()
883 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); in sdma_v4_0_gfx_enable()
911 u32 rb_cntl, ib_cntl; in sdma_v4_0_page_stop() local
917 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); in sdma_v4_0_page_stop()
918 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, in sdma_v4_0_page_stop()
920 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); in sdma_v4_0_page_stop()
1020 sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) sdma_v4_0_rb_cntl() argument
1046 u32 rb_cntl, ib_cntl, wptr_poll_cntl; sdma_v4_0_gfx_resume() local
1131 u32 rb_cntl, ib_cntl, wptr_poll_cntl; sdma_v4_0_page_resume() local
[all...]
H A Dsdma_v3_0.c513 u32 rb_cntl, ib_cntl; in sdma_v3_0_gfx_stop() local
519 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_stop()
520 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v3_0_gfx_stop()
521 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v3_0_gfx_stop()
640 u32 rb_cntl, ib_cntl, wptr_poll_cntl; in sdma_v3_0_gfx_resume() local
667 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_resume()
668 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v3_0_gfx_resume()
670 rb_cntl in sdma_v3_0_gfx_resume()
[all...]
H A Dsdma_v2_4.c339 u32 rb_cntl, ib_cntl; in sdma_v2_4_gfx_stop() local
345 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_stop()
346 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v2_4_gfx_stop()
347 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v2_4_gfx_stop()
405 u32 rb_cntl, ib_cntl; in sdma_v2_4_gfx_resume() local
429 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_resume()
430 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v2_4_gfx_resume()
432 rb_cntl in sdma_v2_4_gfx_resume()
[all...]
H A Dsdma_v6_0.c381 u32 rb_cntl, ib_cntl; in sdma_v6_0_gfx_stop() local
387 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); in sdma_v6_0_gfx_stop()
388 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0); in sdma_v6_0_gfx_stop()
389 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); in sdma_v6_0_gfx_stop()
470 u32 rb_cntl, ib_cntl; in sdma_v6_0_gfx_resume() local
486 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); in sdma_v6_0_gfx_resume()
487 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v6_0_gfx_resume()
489 rb_cntl in sdma_v6_0_gfx_resume()
[all...]
H A Dsi_dma.c115 u32 rb_cntl; in si_dma_stop() local
122 rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); in si_dma_stop()
123 rb_cntl &= ~DMA_RB_ENABLE; in si_dma_stop()
124 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_stop()
131 u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; in si_dma_start() local
143 rb_cntl = rb_bufsz << 1; in si_dma_start()
145 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; in si_dma_start()
147 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_start()
158 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; in si_dma_start()
175 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABL in si_dma_start()
[all...]
H A Dsdma_v5_0.c559 u32 rb_cntl, ib_cntl; in sdma_v5_0_gfx_stop() local
565 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_gfx_stop()
566 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v5_0_gfx_stop()
567 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_0_gfx_stop()
683 u32 rb_cntl, ib_cntl; in sdma_v5_0_gfx_resume() local
700 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_gfx_resume()
701 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v5_0_gfx_resume()
703 rb_cntl in sdma_v5_0_gfx_resume()
[all...]
H A Dsdma_v5_2.c364 u32 rb_cntl, ib_cntl; in sdma_v5_2_gfx_stop() local
370 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_2_gfx_stop()
371 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v5_2_gfx_stop()
372 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_2_gfx_stop()
486 u32 rb_cntl, ib_cntl; in sdma_v5_2_gfx_resume() local
503 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_2_gfx_resume()
504 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v5_2_gfx_resume()
506 rb_cntl in sdma_v5_2_gfx_resume()
[all...]
H A Dcik_sdma.c308 u32 rb_cntl; in cik_sdma_gfx_stop() local
314 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in cik_sdma_gfx_stop()
315 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK; in cik_sdma_gfx_stop()
316 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in cik_sdma_gfx_stop()
429 u32 rb_cntl, ib_cntl; in cik_sdma_gfx_resume() local
455 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
457 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | in cik_sdma_gfx_resume()
460 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in cik_sdma_gfx_resume()
474 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; in cik_sdma_gfx_resume()
484 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MAS in cik_sdma_gfx_resume()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v4_0.c960 u32 rb_cntl, ib_cntl; in sdma_v4_0_gfx_stop() local
971 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); in sdma_v4_0_gfx_stop()
972 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v4_0_gfx_stop()
973 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); in sdma_v4_0_gfx_stop()
1002 u32 rb_cntl, ib_cntl; in sdma_v4_0_page_stop() local
1015 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); in sdma_v4_0_page_stop()
1016 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, in sdma_v4_0_page_stop()
1018 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); in sdma_v4_0_page_stop()
1116 sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) sdma_v4_0_rb_cntl() argument
1142 u32 rb_cntl, ib_cntl, wptr_poll_cntl; sdma_v4_0_gfx_resume() local
1232 u32 rb_cntl, ib_cntl, wptr_poll_cntl; sdma_v4_0_page_resume() local
[all...]
H A Dsdma_v2_4.c343 u32 rb_cntl, ib_cntl; in sdma_v2_4_gfx_stop() local
351 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_stop()
352 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v2_4_gfx_stop()
353 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v2_4_gfx_stop()
411 u32 rb_cntl, ib_cntl; in sdma_v2_4_gfx_resume() local
437 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_resume()
438 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v2_4_gfx_resume()
440 rb_cntl in sdma_v2_4_gfx_resume()
[all...]
H A Dsi_dma.c115 u32 rb_cntl; in si_dma_stop() local
121 rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); in si_dma_stop()
122 rb_cntl &= ~DMA_RB_ENABLE; in si_dma_stop()
123 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_stop()
133 u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; in si_dma_start() local
145 rb_cntl = rb_bufsz << 1; in si_dma_start()
147 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; in si_dma_start()
149 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_start()
160 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; in si_dma_start()
177 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABL in si_dma_start()
[all...]
H A Dsdma_v5_2.c462 u32 rb_cntl, ib_cntl; in sdma_v5_2_gfx_stop() local
472 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_2_gfx_stop()
473 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v5_2_gfx_stop()
474 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_2_gfx_stop() local
583 u32 rb_cntl, ib_cntl; in sdma_v5_2_gfx_resume() local
601 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_2_gfx_resume()
602 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v5_2_gfx_resume()
604 rb_cntl in sdma_v5_2_gfx_resume()
608 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); sdma_v5_2_gfx_resume() local
706 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); sdma_v5_2_gfx_resume() local
[all...]
H A Dsdma_v5_0.c526 u32 rb_cntl, ib_cntl; in sdma_v5_0_gfx_stop() local
534 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_gfx_stop()
535 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v5_0_gfx_stop()
536 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_0_gfx_stop() local
652 u32 rb_cntl, ib_cntl; in sdma_v5_0_gfx_resume() local
671 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_gfx_resume()
672 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v5_0_gfx_resume()
674 rb_cntl in sdma_v5_0_gfx_resume()
678 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); sdma_v5_0_gfx_resume() local
775 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); sdma_v5_0_gfx_resume() local
[all...]
H A Dsdma_v3_0.c517 u32 rb_cntl, ib_cntl; in sdma_v3_0_gfx_stop() local
525 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_stop()
526 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v3_0_gfx_stop()
527 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in sdma_v3_0_gfx_stop()
646 u32 rb_cntl, ib_cntl, wptr_poll_cntl; in sdma_v3_0_gfx_resume() local
675 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_resume()
676 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v3_0_gfx_resume()
678 rb_cntl in sdma_v3_0_gfx_resume()
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H A Dcik_sdma.c310 u32 rb_cntl; in cik_sdma_gfx_stop() local
318 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); in cik_sdma_gfx_stop()
319 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK; in cik_sdma_gfx_stop()
320 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in cik_sdma_gfx_stop()
433 u32 rb_cntl, ib_cntl; in cik_sdma_gfx_resume() local
461 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
463 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | in cik_sdma_gfx_resume()
466 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); in cik_sdma_gfx_resume()
480 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; in cik_sdma_gfx_resume()
490 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MAS in cik_sdma_gfx_resume()
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