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Searched refs:mdp4_dma (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4.xml.h89 enum mdp4_dma { enum
447 static inline uint32_t __offset_DMA(enum mdp4_dma idx) in __offset_DMA()
456 static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } in REG_MDP4_DMA()
458 static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } in REG_MDP4_DMA_CONFIG()
487 static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0); } in REG_MDP4_DMA_SRC_SIZE()
501 static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0); } in REG_MDP4_DMA_SRC_BASE()
503 static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0); } in REG_MDP4_DMA_SRC_STRIDE()
505 static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0); } in REG_MDP4_DMA_DST_SIZE()
519 static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0); } in REG_MDP4_DMA_CURSOR_SIZE()
533 static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i
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H A Dmdp4_kms.h81 static inline uint32_t dma2irq(enum mdp4_dma dma) in dma2irq()
91 static inline uint32_t dma2err(enum mdp4_dma dma) in dma2err()
195 enum mdp4_dma dma_id);
H A Dmdp4_crtc.c20 enum mdp4_dma dma;
228 enum mdp4_dma dma = mdp4_crtc->dma; in mdp4_crtc_mode_set_nofb()
368 enum mdp4_dma dma = mdp4_crtc->dma; in update_cursor()
630 enum mdp4_dma dma_id) in mdp4_crtc_init()
H A Dmdp4_kms.c312 static const enum mdp4_dma mdp4_crtcs[] = { in modeset_init()
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4.xml.h96 enum mdp4_dma { enum
454 static inline uint32_t __offset_DMA(enum mdp4_dma idx) in __offset_DMA()
463 static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } in REG_MDP4_DMA()
465 static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } in REG_MDP4_DMA_CONFIG()
494 static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0); } in REG_MDP4_DMA_SRC_SIZE()
508 static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0); } in REG_MDP4_DMA_SRC_BASE()
510 static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0); } in REG_MDP4_DMA_SRC_STRIDE()
512 static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0); } in REG_MDP4_DMA_DST_SIZE()
526 static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0); } in REG_MDP4_DMA_CURSOR_SIZE()
540 static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i
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H A Dmdp4_kms.h75 static inline uint32_t dma2irq(enum mdp4_dma dma) in dma2irq()
85 static inline uint32_t dma2err(enum mdp4_dma dma) in dma2err()
189 enum mdp4_dma dma_id);
H A Dmdp4_crtc.c21 enum mdp4_dma dma;
229 enum mdp4_dma dma = mdp4_crtc->dma; in mdp4_crtc_mode_set_nofb()
369 enum mdp4_dma dma = mdp4_crtc->dma; in update_cursor()
631 enum mdp4_dma dma_id) in mdp4_crtc_init()
H A Dmdp4_kms.c294 static const enum mdp4_dma mdp4_crtcs[] = { in modeset_init()

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