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Searched refs:mask1 (Results 1 - 25 of 129) sorted by relevance

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/kernel/linux/linux-6.6/tools/testing/selftests/bpf/progs/
H A Dcpumask_success.c27 struct bpf_cpumask *mask1, *mask2, *mask3, *mask4; in create_cpumask_set() local
29 mask1 = create_cpumask(); in create_cpumask_set()
30 if (!mask1) in create_cpumask_set()
35 bpf_cpumask_release(mask1); in create_cpumask_set()
42 bpf_cpumask_release(mask1); in create_cpumask_set()
50 bpf_cpumask_release(mask1); in create_cpumask_set()
57 *out1 = mask1; in create_cpumask_set()
181 struct bpf_cpumask *mask1, *mask2; in BPF_PROG() local
187 mask1 = create_cpumask(); in BPF_PROG()
188 if (!mask1) in BPF_PROG()
245 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; BPF_PROG() local
292 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; BPF_PROG() local
334 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; BPF_PROG() local
467 struct bpf_cpumask *mask1, *mask2; BPF_PROG() local
[all...]
/kernel/linux/linux-5.10/sound/pci/ice1712/
H A Dwm8776.c139 .mask1 = WM8776_DACVOL_MASK,
149 .mask1 = WM8776_DAC_PL_LL,
157 .mask1 = WM8776_DAC_DZCEN,
165 .mask1 = WM8776_HPVOL_MASK,
175 .mask1 = WM8776_PWR_HPPD,
183 .mask1 = WM8776_VOL_HPZCEN,
191 .mask1 = WM8776_OUTMUX_AUX,
197 .mask1 = WM8776_OUTMUX_BYPASS,
203 .mask1 = WM8776_DAC_IZD,
210 .mask1
[all...]
H A Dwm8766.c36 .mask1 = WM8766_VOL_MASK,
47 .mask1 = WM8766_VOL_MASK,
58 .mask1 = WM8766_VOL_MASK,
67 .mask1 = WM8766_DAC2_MUTE1,
74 .mask1 = WM8766_DAC2_MUTE2,
81 .mask1 = WM8766_DAC2_MUTE3,
88 .mask1 = WM8766_PHASE_INVERT1,
94 .mask1 = WM8766_PHASE_INVERT2,
100 .mask1 = WM8766_PHASE_INVERT3,
106 .mask1
[all...]
/kernel/linux/linux-6.6/sound/pci/ice1712/
H A Dwm8776.c135 .mask1 = WM8776_DACVOL_MASK,
145 .mask1 = WM8776_DAC_PL_LL,
153 .mask1 = WM8776_DAC_DZCEN,
161 .mask1 = WM8776_HPVOL_MASK,
171 .mask1 = WM8776_PWR_HPPD,
179 .mask1 = WM8776_VOL_HPZCEN,
187 .mask1 = WM8776_OUTMUX_AUX,
193 .mask1 = WM8776_OUTMUX_BYPASS,
199 .mask1 = WM8776_DAC_IZD,
206 .mask1
[all...]
H A Dwm8766.c36 .mask1 = WM8766_VOL_MASK,
47 .mask1 = WM8766_VOL_MASK,
58 .mask1 = WM8766_VOL_MASK,
67 .mask1 = WM8766_DAC2_MUTE1,
74 .mask1 = WM8766_DAC2_MUTE2,
81 .mask1 = WM8766_DAC2_MUTE3,
88 .mask1 = WM8766_PHASE_INVERT1,
94 .mask1 = WM8766_PHASE_INVERT2,
100 .mask1 = WM8766_PHASE_INVERT3,
106 .mask1
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/
H A Ddc_helper.c110 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in set_reg_field_values()
118 field_value1, mask1, shift1); in set_reg_field_values()
225 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in generic_reg_update_ex()
234 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, in generic_reg_update_ex()
253 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in generic_reg_set_ex()
261 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, in generic_reg_set_ex()
289 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get2()
293 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); in generic_reg_get2()
299 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get3()
304 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift in generic_reg_get3()
108 set_reg_field_values(struct dc_reg_value_masks *field_value_mask, uint32_t addr, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, va_list ap) set_reg_field_values() argument
223 generic_reg_update_ex(const struct dc_context *ctx, uint32_t addr, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) generic_reg_update_ex() argument
251 generic_reg_set_ex(const struct dc_context *ctx, uint32_t addr, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) generic_reg_set_ex() argument
288 generic_reg_get2(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2) generic_reg_get2() argument
298 generic_reg_get3(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3) generic_reg_get3() argument
310 generic_reg_get4(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4) generic_reg_get4() argument
324 generic_reg_get5(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5) generic_reg_get5() argument
340 generic_reg_get6(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6) generic_reg_get6() argument
358 generic_reg_get7(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6, uint8_t shift7, uint32_t mask7, uint32_t *field_value7) generic_reg_get7() argument
378 generic_reg_get8(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6, uint8_t shift7, uint32_t mask7, uint32_t *field_value7, uint8_t shift8, uint32_t mask8, uint32_t *field_value8) generic_reg_get8() argument
508 generic_indirect_reg_get(const struct dc_context *ctx, uint32_t addr_index, uint32_t addr_data, uint32_t index, int n, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, ...) generic_indirect_reg_get() argument
539 generic_indirect_reg_update_ex(const struct dc_context *ctx, uint32_t addr_index, uint32_t addr_data, uint32_t index, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) generic_indirect_reg_update_ex() argument
570 generic_indirect_reg_update_ex_sync(const struct dc_context *ctx, uint32_t index, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) generic_indirect_reg_update_ex_sync() argument
599 generic_indirect_reg_get_sync(const struct dc_context *ctx, uint32_t index, int n, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, ...) generic_indirect_reg_get_sync() argument
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.c45 uint32_t mask1, uint32_t field_value1, in set_reg_field_values()
52 set_reg_field_value_masks(field_value_mask, field_value1, mask1, in set_reg_field_values()
73 uint32_t mask1, uint32_t field_value1, ...) in dmub_reg_update()
80 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, in dmub_reg_update()
90 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) in dmub_reg_set()
96 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, in dmub_reg_set()
43 set_reg_field_values(struct dmub_reg_value_masks *field_value_mask, uint32_t addr, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, va_list ap) set_reg_field_values() argument
72 dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) dmub_reg_update() argument
89 dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) dmub_reg_set() argument
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.c45 uint32_t mask1, uint32_t field_value1, in set_reg_field_values()
52 set_reg_field_value_masks(field_value_mask, field_value1, mask1, in set_reg_field_values()
73 uint32_t mask1, uint32_t field_value1, ...) in dmub_reg_update()
80 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, in dmub_reg_update()
90 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) in dmub_reg_set()
96 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, in dmub_reg_set()
43 set_reg_field_values(struct dmub_reg_value_masks *field_value_mask, uint32_t addr, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, va_list ap) set_reg_field_values() argument
72 dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) dmub_reg_update() argument
89 dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) dmub_reg_set() argument
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/
H A Ddc_helper.c127 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in set_reg_field_values()
135 field_value1, mask1, shift1); in set_reg_field_values()
244 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in generic_reg_update_ex()
253 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, in generic_reg_update_ex()
272 uint8_t shift1, uint32_t mask1, uint32_t field_value1, in generic_reg_set_ex()
280 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, in generic_reg_set_ex()
334 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get2()
338 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); in generic_reg_get2()
344 uint8_t shift1, uint32_t mask1, uint32_t *field_value1, in generic_reg_get3()
349 *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift in generic_reg_get3()
125 set_reg_field_values(struct dc_reg_value_masks *field_value_mask, uint32_t addr, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, va_list ap) set_reg_field_values() argument
242 generic_reg_update_ex(const struct dc_context *ctx, uint32_t addr, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) generic_reg_update_ex() argument
270 generic_reg_set_ex(const struct dc_context *ctx, uint32_t addr, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) generic_reg_set_ex() argument
333 generic_reg_get2(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2) generic_reg_get2() argument
343 generic_reg_get3(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3) generic_reg_get3() argument
355 generic_reg_get4(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4) generic_reg_get4() argument
369 generic_reg_get5(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5) generic_reg_get5() argument
385 generic_reg_get6(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6) generic_reg_get6() argument
403 generic_reg_get7(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6, uint8_t shift7, uint32_t mask7, uint32_t *field_value7) generic_reg_get7() argument
423 generic_reg_get8(const struct dc_context *ctx, uint32_t addr, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, uint8_t shift2, uint32_t mask2, uint32_t *field_value2, uint8_t shift3, uint32_t mask3, uint32_t *field_value3, uint8_t shift4, uint32_t mask4, uint32_t *field_value4, uint8_t shift5, uint32_t mask5, uint32_t *field_value5, uint8_t shift6, uint32_t mask6, uint32_t *field_value6, uint8_t shift7, uint32_t mask7, uint32_t *field_value7, uint8_t shift8, uint32_t mask8, uint32_t *field_value8) generic_reg_get8() argument
555 generic_indirect_reg_get(const struct dc_context *ctx, uint32_t addr_index, uint32_t addr_data, uint32_t index, int n, uint8_t shift1, uint32_t mask1, uint32_t *field_value1, ...) generic_indirect_reg_get() argument
586 generic_indirect_reg_update_ex(const struct dc_context *ctx, uint32_t addr_index, uint32_t addr_data, uint32_t index, uint32_t reg_val, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) generic_indirect_reg_update_ex() argument
[all...]
/kernel/linux/linux-5.10/fs/orangefs/
H A Dorangefs-debugfs.c63 __u64 mask1; member
456 c_mask.mask1, in orangefs_debug_write()
543 (unsigned long long *)&(cdm_array[i].mask1), in orangefs_prepare_cdm_array()
755 if ((mask->mask1 & cdm_array[index].mask1) || in do_c_string()
799 if ((c_mask->mask1 == cdm_array[client_all_index].mask1) && in check_amalgam_keyword()
806 if ((c_mask->mask1 == cdm_array[client_verbose_index].mask1) && in check_amalgam_keyword()
875 (**sane_mask).mask1 in do_c_mask()
[all...]
/kernel/linux/linux-6.6/fs/orangefs/
H A Dorangefs-debugfs.c63 __u64 mask1; member
456 c_mask.mask1, in orangefs_debug_write()
543 (unsigned long long *)&(cdm_array[i].mask1), in orangefs_prepare_cdm_array()
755 if ((mask->mask1 & cdm_array[index].mask1) || in do_c_string()
799 if ((c_mask->mask1 == cdm_array[client_all_index].mask1) && in check_amalgam_keyword()
806 if ((c_mask->mask1 == cdm_array[client_verbose_index].mask1) && in check_amalgam_keyword()
875 (**sane_mask).mask1 in do_c_mask()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/irq/dcn30/
H A Dirq_service_dcn30.c220 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
223 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
225 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
226 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
234 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
237 reg1 ## __ ## mask1 ## _MASK,\
239 reg1 ## __ ## mask1 ## _MASK,\
240 ~reg1 ## __ ## mask1 ## _MASK \
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/irq/dcn21/
H A Dirq_service_dcn21.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
220 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
221 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
232 reg1 ## __ ## mask1 ## _MASK,\
234 reg1 ## __ ## mask1 ## _MASK,\
235 ~reg1 ## __ ## mask1 ## _MASK \
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/irq/dcn315/
H A Dirq_service_dcn315.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
220 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
221 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
232 reg1 ## __ ## mask1 ## _MASK,\
234 reg1 ## __ ## mask1 ## _MASK,\
235 ~reg1 ## __ ## mask1 ## _MASK \
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/irq/dcn314/
H A Dirq_service_dcn314.c210 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
215 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
216 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
224 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
227 reg1 ## __ ## mask1 ## _MASK,\
229 reg1 ## __ ## mask1 ## _MASK,\
230 ~reg1 ## __ ## mask1 ## _MASK \
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/irq/dcn31/
H A Dirq_service_dcn31.c208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
211 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
214 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
222 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
225 reg1 ## __ ## mask1 ## _MASK,\
227 reg1 ## __ ## mask1 ## _MASK,\
228 ~reg1 ## __ ## mask1 ## _MASK \
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/irq/dcn302/
H A Dirq_service_dcn302.c195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
197 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
200 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
216 reg1 ## __ ## mask1 ## _MASK,\
218 reg1 ## __ ## mask1 ## _MASK,\
219 ~reg1 ## __ ## mask1 ## _MASK \
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/irq/dcn32/
H A Dirq_service_dcn32.c209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
212 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
214 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
215 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
226 reg1 ## __ ## mask1 ## _MASK,\
228 reg1 ## __ ## mask1 ## _MASK,\
229 ~reg1 ## __ ## mask1 ## _MASK \
/kernel/linux/linux-5.10/arch/mips/sgi-ip27/
H A Dip27-nmi.c134 u64 mask0, mask1, pend0, pend1; in nmi_dump_hub_irq() local
138 mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_A); in nmi_dump_hub_irq()
141 mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_B); in nmi_dump_hub_irq()
147 pr_emerg("PI_INT_MASK0: %16llx PI_INT_MASK1: %16llx\n", mask0, mask1); in nmi_dump_hub_irq()
/kernel/linux/linux-5.10/arch/alpha/kernel/
H A Dsys_rawhide.c102 unsigned int mask, mask1, hose; in rawhide_mask_and_ack_irq() local
111 mask1 = 1 << irq; in rawhide_mask_and_ack_irq()
112 mask = ~mask1 | hose_irq_masks[hose]; in rawhide_mask_and_ack_irq()
121 *(vuip)MCPCIA_INT_REQ(MCPCIA_HOSE2MID(hose)) = mask1; in rawhide_mask_and_ack_irq()
/kernel/linux/linux-6.6/arch/alpha/kernel/
H A Dsys_rawhide.c102 unsigned int mask, mask1, hose; in rawhide_mask_and_ack_irq() local
111 mask1 = 1 << irq; in rawhide_mask_and_ack_irq()
112 mask = ~mask1 | hose_irq_masks[hose]; in rawhide_mask_and_ack_irq()
121 *(vuip)MCPCIA_INT_REQ(MCPCIA_HOSE2MID(hose)) = mask1; in rawhide_mask_and_ack_irq()
/kernel/linux/linux-6.6/arch/mips/sgi-ip27/
H A Dip27-nmi.c134 u64 mask0, mask1, pend0, pend1; in nmi_dump_hub_irq() local
138 mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_A); in nmi_dump_hub_irq()
141 mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_B); in nmi_dump_hub_irq()
147 pr_emerg("PI_INT_MASK0: %16llx PI_INT_MASK1: %16llx\n", mask0, mask1); in nmi_dump_hub_irq()
/kernel/linux/linux-5.10/drivers/soc/fsl/qe/
H A Dgpio.c248 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1)); in qe_pin_set_dedicated() local
267 if (sregs->cpdata & mask1) in qe_pin_set_dedicated()
268 qe_gc->cpdata |= mask1; in qe_pin_set_dedicated()
270 qe_gc->cpdata &= ~mask1; in qe_pin_set_dedicated()
273 qe_clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1); in qe_pin_set_dedicated()
/kernel/linux/linux-6.6/drivers/soc/fsl/qe/
H A Dgpio.c241 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1)); in qe_pin_set_dedicated() local
260 if (sregs->cpdata & mask1) in qe_pin_set_dedicated()
261 qe_gc->cpdata |= mask1; in qe_pin_set_dedicated()
263 qe_gc->cpdata &= ~mask1; in qe_pin_set_dedicated()
266 qe_clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1); in qe_pin_set_dedicated()
/kernel/linux/linux-5.10/arch/parisc/kernel/
H A Dsys_parisc32.c28 compat_uint_t mask0, compat_uint_t mask1, compat_int_t dfd, in sys32_fanotify_mark()
32 ((__u64)mask1 << 32) | mask0, in sys32_fanotify_mark()
27 sys32_fanotify_mark(compat_int_t fanotify_fd, compat_uint_t flags, compat_uint_t mask0, compat_uint_t mask1, compat_int_t dfd, const char __user * pathname) sys32_fanotify_mark() argument

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