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Searched refs:kiq (Results 1 - 25 of 42) sorted by relevance

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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_gfx.c310 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; in amdgpu_gfx_kiq_init_ring() local
313 spin_lock_init(&kiq->ring_lock); in amdgpu_gfx_kiq_init_ring()
321 (adev->doorbell_index.kiq + in amdgpu_gfx_kiq_init_ring()
329 ring->eop_gpu_addr = kiq->eop_gpu_addr; in amdgpu_gfx_kiq_init_ring()
335 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r); in amdgpu_gfx_kiq_init_ring()
347 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; in amdgpu_gfx_kiq_fini() local
349 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq in amdgpu_gfx_kiq_fini()
357 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; amdgpu_gfx_kiq_init() local
383 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; amdgpu_gfx_mqd_sw_init() local
474 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; amdgpu_gfx_mqd_sw_fini() local
504 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; amdgpu_gfx_disable_kcq() local
535 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; amdgpu_gfx_disable_kgq() local
581 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; amdgpu_gfx_enable_kcq() local
638 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; amdgpu_gfx_enable_kgq() local
925 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; amdgpu_kiq_rreg() local
993 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; amdgpu_kiq_wreg() local
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H A Damdgpu_amdkfd.c823 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; in amdgpu_amdkfd_unmap_hiq() local
824 struct amdgpu_ring *kiq_ring = &kiq->ring; in amdgpu_amdkfd_unmap_hiq()
829 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) in amdgpu_amdkfd_unmap_hiq()
846 spin_lock(&kiq->ring_lock); in amdgpu_amdkfd_unmap_hiq()
848 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { in amdgpu_amdkfd_unmap_hiq()
849 spin_unlock(&kiq->ring_lock); in amdgpu_amdkfd_unmap_hiq()
854 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 0, 0); in amdgpu_amdkfd_unmap_hiq()
859 spin_unlock(&kiq in amdgpu_amdkfd_unmap_hiq()
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H A Dmes_v11_0.c877 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in mes_v11_0_kiq_enable_queue() local
878 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in mes_v11_0_kiq_enable_queue()
881 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) in mes_v11_0_kiq_enable_queue()
884 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); in mes_v11_0_kiq_enable_queue()
890 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); in mes_v11_0_kiq_enable_queue()
902 ring = &adev->gfx.kiq[0].ring; in mes_v11_0_queue_init()
969 spin_lock_init(&adev->gfx.kiq[0].ring_lock); in mes_v11_0_kiq_ring_init()
971 ring = &adev->gfx.kiq[ in mes_v11_0_kiq_ring_init()
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H A Dmes_v10_1.c803 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in mes_v10_1_kiq_enable_queue() local
804 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in mes_v10_1_kiq_enable_queue()
807 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) in mes_v10_1_kiq_enable_queue()
810 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); in mes_v10_1_kiq_enable_queue()
816 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); in mes_v10_1_kiq_enable_queue()
863 spin_lock_init(&adev->gfx.kiq[0].ring_lock); in mes_v10_1_kiq_ring_init()
865 ring = &adev->gfx.kiq[0].ring; in mes_v10_1_kiq_ring_init()
891 ring = &adev->gfx.kiq[ in mes_v10_1_mqd_sw_init()
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H A Dgmc_v10_0.c337 * Directly use kiq to do the vm invalidation instead in gmc_v10_0_flush_gpu_tlb()
339 if (adev->gfx.kiq[0].ring.sched.ready && !adev->enable_mes && in gmc_v10_0_flush_gpu_tlb()
425 struct amdgpu_ring *ring = &adev->gfx.kiq[0].ring; in gmc_v10_0_flush_gpu_tlb_pasid()
426 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in gmc_v10_0_flush_gpu_tlb_pasid() local
429 spin_lock(&adev->gfx.kiq[0].ring_lock); in gmc_v10_0_flush_gpu_tlb_pasid()
431 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); in gmc_v10_0_flush_gpu_tlb_pasid()
432 kiq->pmf->kiq_invalidate_tlbs(ring, in gmc_v10_0_flush_gpu_tlb_pasid()
437 spin_unlock(&adev->gfx.kiq[0].ring_lock); in gmc_v10_0_flush_gpu_tlb_pasid()
442 spin_unlock(&adev->gfx.kiq[ in gmc_v10_0_flush_gpu_tlb_pasid()
[all...]
H A Dgmc_v11_0.c295 * Directly use kiq to do the vm invalidation instead in gmc_v11_0_flush_gpu_tlb()
297 if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring.sched.ready) && in gmc_v11_0_flush_gpu_tlb()
335 struct amdgpu_ring *ring = &adev->gfx.kiq[0].ring; in gmc_v11_0_flush_gpu_tlb_pasid()
336 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in gmc_v11_0_flush_gpu_tlb_pasid() local
339 spin_lock(&adev->gfx.kiq[0].ring_lock); in gmc_v11_0_flush_gpu_tlb_pasid()
341 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); in gmc_v11_0_flush_gpu_tlb_pasid()
342 kiq->pmf->kiq_invalidate_tlbs(ring, in gmc_v11_0_flush_gpu_tlb_pasid()
347 spin_unlock(&adev->gfx.kiq[0].ring_lock); in gmc_v11_0_flush_gpu_tlb_pasid()
352 spin_unlock(&adev->gfx.kiq[ in gmc_v11_0_flush_gpu_tlb_pasid()
[all...]
H A Dgmc_v9_0.c847 if (adev->gfx.kiq[0].ring.sched.ready && in gmc_v9_0_flush_gpu_tlb()
956 struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring; in gmc_v9_0_flush_gpu_tlb_pasid()
957 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; in gmc_v9_0_flush_gpu_tlb_pasid() local
972 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8; in gmc_v9_0_flush_gpu_tlb_pasid()
975 ndw += kiq->pmf->invalidate_tlbs_size; in gmc_v9_0_flush_gpu_tlb_pasid()
977 spin_lock(&adev->gfx.kiq[inst].ring_lock); in gmc_v9_0_flush_gpu_tlb_pasid()
981 kiq->pmf->kiq_invalidate_tlbs(ring, in gmc_v9_0_flush_gpu_tlb_pasid()
987 kiq->pmf->kiq_invalidate_tlbs(ring, in gmc_v9_0_flush_gpu_tlb_pasid()
990 kiq in gmc_v9_0_flush_gpu_tlb_pasid()
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H A Dgfx_v9_0.c893 adev->gfx.kiq[0].pmf = &gfx_v9_0_kiq_pm4_funcs; in gfx_v9_0_set_kiq_pm4_funcs()
2001 struct amdgpu_kiq *kiq; in gfx_v9_0_sw_init() local
2154 kiq = &adev->gfx.kiq[0]; in gfx_v9_0_sw_init()
2155 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0); in gfx_v9_0_sw_init()
2196 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); in gfx_v9_0_sw_fini()
3169 adev->gfx.kiq[0].ring.sched.ready = false; in gfx_v9_0_cp_compute_enable()
3368 * so only kiq need set this field. in gfx_v9_0_mqd_init()
3451 (adev->doorbell_index.kiq * in gfx_v9_0_kiq_init_register()
3925 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; gfx_v9_0_kiq_read_clock() local
5461 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; gfx_v9_0_ring_preempt_ib() local
[all...]
H A Damdgpu_virt.c78 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in amdgpu_virt_kiq_reg_write_reg_wait() local
79 struct amdgpu_ring *ring = &kiq->ring; in amdgpu_virt_kiq_reg_write_reg_wait()
90 spin_lock_irqsave(&kiq->ring_lock, flags); in amdgpu_virt_kiq_reg_write_reg_wait()
99 spin_unlock_irqrestore(&kiq->ring_lock, flags); in amdgpu_virt_kiq_reg_write_reg_wait()
121 spin_unlock_irqrestore(&kiq->ring_lock, flags); in amdgpu_virt_kiq_reg_write_reg_wait()
H A Damdgpu_amdkfd_gfx_v10_3.c280 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in hiq_mqd_load_v10_3()
295 spin_lock(&adev->gfx.kiq[0].ring_lock); in hiq_mqd_load_v10_3()
322 spin_unlock(&adev->gfx.kiq[0].ring_lock); in hiq_mqd_load_v10_3()
H A Dgfx_v9_4_3.c189 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; in gfx_v9_4_3_set_kiq_pm4_funcs()
781 struct amdgpu_kiq *kiq; in gfx_v9_4_3_sw_init() local
850 kiq = &adev->gfx.kiq[xcc_id]; in gfx_v9_4_3_sw_init()
851 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, xcc_id); in gfx_v9_4_3_sw_init()
888 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); in gfx_v9_4_3_sw_fini()
1389 adev->gfx.kiq[xcc_id].ring.sched.ready = false; in gfx_v9_4_3_xcc_cp_compute_enable()
1590 * so only kiq need set this field. in gfx_v9_4_3_xcc_mqd_init()
1676 ((adev->doorbell_index.kiq in gfx_v9_4_3_xcc_kiq_init_register()
[all...]
H A Dvega20_reg_init.c60 adev->doorbell_index.kiq = AMDGPU_VEGA20_DOORBELL_KIQ; in vega20_doorbell_index_init()
H A Dvega10_reg_init.c60 adev->doorbell_index.kiq = AMDGPU_DOORBELL64_KIQ; in vega10_doorbell_index_init()
H A Dgfx_v11_0.c199 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx11_kiq_unmap_queues()
267 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; in gfx_v11_0_set_kiq_pm4_funcs()
1309 struct amdgpu_kiq *kiq; in gfx_v11_0_sw_init() local
1443 kiq = &adev->gfx.kiq[0]; in gfx_v11_0_sw_init()
1444 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0); in gfx_v11_0_sw_init()
1514 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); in gfx_v11_0_sw_fini()
3590 (adev->doorbell_index.kiq * 2) << 2); in gfx_v11_0_cp_set_doorbell_range()
3948 (adev->doorbell_index.kiq * in gfx_v11_0_kiq_init_register()
5542 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; gfx_v11_0_ring_preempt_ib() local
[all...]
H A Damdgpu_amdkfd_gfx_v10.c294 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; in kgd_hiq_mqd_load()
309 spin_lock(&adev->gfx.kiq[0].ring_lock); in kgd_hiq_mqd_load()
336 spin_unlock(&adev->gfx.kiq[0].ring_lock); in kgd_hiq_mqd_load()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_gfx.c295 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_gfx_kiq_init_ring() local
298 spin_lock_init(&kiq->ring_lock); in amdgpu_gfx_kiq_init_ring()
303 ring->doorbell_index = adev->doorbell_index.kiq; in amdgpu_gfx_kiq_init_ring()
309 ring->eop_gpu_addr = kiq->eop_gpu_addr; in amdgpu_gfx_kiq_init_ring()
316 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r); in amdgpu_gfx_kiq_init_ring()
328 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_gfx_kiq_fini() local
330 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq in amdgpu_gfx_kiq_fini()
338 struct amdgpu_kiq *kiq = &adev->gfx.kiq; amdgpu_gfx_kiq_init() local
463 struct amdgpu_kiq *kiq = &adev->gfx.kiq; amdgpu_gfx_disable_kcq() local
496 struct amdgpu_kiq *kiq = &adev->gfx.kiq; amdgpu_gfx_enable_kcq() local
711 struct amdgpu_kiq *kiq = &adev->gfx.kiq; amdgpu_kiq_rreg() local
776 struct amdgpu_kiq *kiq = &adev->gfx.kiq; amdgpu_kiq_wreg() local
[all...]
H A Dgmc_v10_0.c286 * Directly use kiq to do the vm invalidation instead in gmc_v10_0_flush_gpu_tlb()
288 if (adev->gfx.kiq.ring.sched.ready && in gmc_v10_0_flush_gpu_tlb()
375 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; in gmc_v10_0_flush_gpu_tlb_pasid()
376 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gmc_v10_0_flush_gpu_tlb_pasid() local
379 spin_lock(&adev->gfx.kiq.ring_lock); in gmc_v10_0_flush_gpu_tlb_pasid()
381 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); in gmc_v10_0_flush_gpu_tlb_pasid()
382 kiq->pmf->kiq_invalidate_tlbs(ring, in gmc_v10_0_flush_gpu_tlb_pasid()
387 spin_unlock(&adev->gfx.kiq.ring_lock); in gmc_v10_0_flush_gpu_tlb_pasid()
392 spin_unlock(&adev->gfx.kiq in gmc_v10_0_flush_gpu_tlb_pasid()
[all...]
H A Dgmc_v9_0.c747 if (adev->gfx.kiq.ring.sched.ready && in gmc_v9_0_flush_gpu_tlb()
843 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; in gmc_v9_0_flush_gpu_tlb_pasid()
844 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gmc_v9_0_flush_gpu_tlb_pasid() local
859 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8; in gmc_v9_0_flush_gpu_tlb_pasid()
862 ndw += kiq->pmf->invalidate_tlbs_size; in gmc_v9_0_flush_gpu_tlb_pasid()
864 spin_lock(&adev->gfx.kiq.ring_lock); in gmc_v9_0_flush_gpu_tlb_pasid()
868 kiq->pmf->kiq_invalidate_tlbs(ring, in gmc_v9_0_flush_gpu_tlb_pasid()
870 kiq->pmf->kiq_invalidate_tlbs(ring, in gmc_v9_0_flush_gpu_tlb_pasid()
875 spin_unlock(&adev->gfx.kiq in gmc_v9_0_flush_gpu_tlb_pasid()
[all...]
H A Damdgpu_virt.c63 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_virt_kiq_reg_write_reg_wait() local
64 struct amdgpu_ring *ring = &kiq->ring; in amdgpu_virt_kiq_reg_write_reg_wait()
69 spin_lock_irqsave(&kiq->ring_lock, flags); in amdgpu_virt_kiq_reg_write_reg_wait()
78 spin_unlock_irqrestore(&kiq->ring_lock, flags); in amdgpu_virt_kiq_reg_write_reg_wait()
100 spin_unlock_irqrestore(&kiq->ring_lock, flags); in amdgpu_virt_kiq_reg_write_reg_wait()
H A Dmes_v10_1.c789 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
790 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
793 if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
796 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
802 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring);
H A Damdgpu_amdkfd_gfx_v10.c310 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in kgd_hiq_mqd_load()
325 spin_lock(&adev->gfx.kiq.ring_lock); in kgd_hiq_mqd_load()
352 spin_unlock(&adev->gfx.kiq.ring_lock); in kgd_hiq_mqd_load()
H A Dvega20_reg_init.c60 adev->doorbell_index.kiq = AMDGPU_VEGA20_DOORBELL_KIQ; in vega20_doorbell_index_init()
H A Dvega10_reg_init.c60 adev->doorbell_index.kiq = AMDGPU_DOORBELL64_KIQ; in vega10_doorbell_index_init()
H A Damdgpu_amdkfd_gfx_v9.c319 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in kgd_gfx_v9_hiq_mqd_load()
334 spin_lock(&adev->gfx.kiq.ring_lock); in kgd_gfx_v9_hiq_mqd_load()
361 spin_unlock(&adev->gfx.kiq.ring_lock); in kgd_gfx_v9_hiq_mqd_load()
H A Damdgpu_amdkfd_gfx_v10_3.c295 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in hiq_mqd_load_v10_3()
310 spin_lock(&adev->gfx.kiq.ring_lock); in hiq_mqd_load_v10_3()
337 spin_unlock(&adev->gfx.kiq.ring_lock); in hiq_mqd_load_v10_3()

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