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Searched refs:gpu_read (Results 1 - 25 of 44) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/panfrost/
H A Dpanfrost_gpu.c25 u32 state = gpu_read(pfdev, GPU_INT_STAT); in panfrost_gpu_irq_handler()
26 u32 fault_status = gpu_read(pfdev, GPU_FAULT_STATUS); in panfrost_gpu_irq_handler()
32 u64 address = (u64) gpu_read(pfdev, GPU_FAULT_ADDRESS_HI) << 32; in panfrost_gpu_irq_handler()
33 address |= gpu_read(pfdev, GPU_FAULT_ADDRESS_LO); in panfrost_gpu_irq_handler()
118 quirks = gpu_read(pfdev, GPU_TILER_CONFIG); in panfrost_gpu_init_quirks()
127 quirks = gpu_read(pfdev, GPU_L2_MMU_CONFIG); in panfrost_gpu_init_quirks()
221 pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES); in panfrost_gpu_init_features()
222 pfdev->features.core_features = gpu_read(pfdev, GPU_CORE_FEATURES); in panfrost_gpu_init_features()
223 pfdev->features.tiler_features = gpu_read(pfdev, GPU_TILER_FEATURES); in panfrost_gpu_init_features()
224 pfdev->features.mem_features = gpu_read(pfde in panfrost_gpu_init_features()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/panfrost/
H A Dpanfrost_gpu.c25 u32 state = gpu_read(pfdev, GPU_INT_STAT); in panfrost_gpu_irq_handler()
26 u32 fault_status = gpu_read(pfdev, GPU_FAULT_STATUS); in panfrost_gpu_irq_handler()
32 u64 address = (u64) gpu_read(pfdev, GPU_FAULT_ADDRESS_HI) << 32; in panfrost_gpu_irq_handler()
33 address |= gpu_read(pfdev, GPU_FAULT_ADDRESS_LO); in panfrost_gpu_irq_handler()
126 quirks = gpu_read(pfdev, GPU_TILER_CONFIG); in panfrost_gpu_init_quirks()
231 pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES); in panfrost_gpu_init_features()
232 pfdev->features.core_features = gpu_read(pfdev, GPU_CORE_FEATURES); in panfrost_gpu_init_features()
233 pfdev->features.tiler_features = gpu_read(pfdev, GPU_TILER_FEATURES); in panfrost_gpu_init_features()
234 pfdev->features.mem_features = gpu_read(pfdev, GPU_MEM_FEATURES); in panfrost_gpu_init_features()
235 pfdev->features.mmu_features = gpu_read(pfde in panfrost_gpu_init_features()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/etnaviv/
H A Detnaviv_gpu.c181 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); in etnaviv_hw_specs()
182 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); in etnaviv_hw_specs()
183 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); in etnaviv_hw_specs()
184 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); in etnaviv_hw_specs()
328 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); in etnaviv_hw_identify()
336 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); in etnaviv_hw_identify()
338 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); in etnaviv_hw_identify()
339 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); in etnaviv_hw_identify()
340 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID); in etnaviv_hw_identify()
347 gpu->identity.product_id = gpu_read(gp in etnaviv_hw_identify()
[all...]
H A Detnaviv_perfmon.c46 return gpu_read(gpu, domain->profile_read); in perf_reg_read()
53 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_reg_read()
62 value += gpu_read(gpu, domain->profile_read); in pipe_reg_read()
84 return gpu_read(gpu, reg); in hi_total_cycle_read()
98 return gpu_read(gpu, reg); in hi_total_idle_cycle_read()
H A Detnaviv_iommu_v2.c172 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE) in etnaviv_iommuv2_restore_nonsec()
196 if (gpu_read(gpu, VIVS_MMUv2_SEC_CONTROL) & VIVS_MMUv2_SEC_CONTROL_ENABLE) in etnaviv_iommuv2_restore_sec()
H A Detnaviv_gpu.h157 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) in gpu_read() function
/kernel/linux/linux-6.6/drivers/gpu/drm/etnaviv/
H A Detnaviv_gpu.c189 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); in etnaviv_hw_specs()
190 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); in etnaviv_hw_specs()
191 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); in etnaviv_hw_specs()
192 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); in etnaviv_hw_specs()
336 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); in etnaviv_hw_identify()
344 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); in etnaviv_hw_identify()
346 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); in etnaviv_hw_identify()
347 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); in etnaviv_hw_identify()
348 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID); in etnaviv_hw_identify()
355 gpu->identity.product_id = gpu_read(gp in etnaviv_hw_identify()
[all...]
H A Detnaviv_perfmon.c46 return gpu_read(gpu, domain->profile_read); in perf_reg_read()
61 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_perf_reg_read()
80 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_reg_read()
86 value += gpu_read(gpu, signal->data); in pipe_reg_read()
106 return gpu_read(gpu, reg); in hi_total_cycle_read()
120 return gpu_read(gpu, reg); in hi_total_idle_cycle_read()
H A Detnaviv_iommu_v2.c172 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE) in etnaviv_iommuv2_restore_nonsec()
196 if (gpu_read(gpu, VIVS_MMUv2_SEC_CONTROL) & VIVS_MMUv2_SEC_CONTROL_ENABLE) in etnaviv_iommuv2_restore_sec()
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/adreno/
H A Da5xx_gpu.c1011 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(i))); in a5xx_recover()
1018 gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD); in a5xx_recover()
1058 if (gpu_read(gpu, REG_A5XX_RBBM_STATUS) & ~A5XX_RBBM_STATUS_HI_BUSY) in _a5xx_check_idle()
1065 return !(gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS) & in _a5xx_check_idle()
1086 gpu_read(gpu, REG_A5XX_RBBM_STATUS), in a5xx_idle()
1087 gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS), in a5xx_idle()
1088 gpu_read(gpu, REG_A5XX_CP_RB_RPTR), in a5xx_idle()
1089 gpu_read(gpu, REG_A5XX_CP_RB_WPTR)); in a5xx_idle()
1102 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(4)), in a5xx_fault_handler()
1103 gpu_read(gp in a5xx_fault_handler()
[all...]
H A Da6xx_gpu.c28 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle()
32 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & in _a6xx_check_idle()
45 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle()
46 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), in a6xx_idle()
47 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), in a6xx_idle()
48 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); in a6xx_idle()
717 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); in a6xx_set_hwcg()
1486 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); in a6xx_dump()
1501 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i))); in a6xx_recover()
1580 val = gpu_read(gp in a6xx_uche_fault_block()
[all...]
H A Da5xx_debugfs.c23 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA)); in pfp_print()
36 gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA)); in me_print()
49 gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA)); in meq_print()
64 val[j] = gpu_read(gpu, REG_A5XX_CP_ROQ_DBG_DATA); in roq_print()
H A Da2xx_gpu.c274 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a2xx_recover()
282 gpu_read(gpu, REG_A2XX_RBBM_SOFT_RESET); in a2xx_recover()
306 if (spin_until(!(gpu_read(gpu, REG_A2XX_RBBM_STATUS) & in a2xx_idle()
321 mstatus = gpu_read(gpu, REG_A2XX_MASTER_INT_SIGNAL); in a2xx_irq()
324 status = gpu_read(gpu, REG_A2XX_MH_INTERRUPT_STATUS); in a2xx_irq()
328 gpu_read(gpu, REG_A2XX_MH_MMU_PAGE_FAULT)); in a2xx_irq()
334 status = gpu_read(gpu, REG_AXXX_CP_INT_STATUS); in a2xx_irq()
344 status = gpu_read(gpu, REG_A2XX_RBBM_INT_STATUS); in a2xx_irq()
451 gpu_read(gpu, REG_A2XX_RBBM_STATUS)); in a2xx_dump()
464 state->rbbm_status = gpu_read(gp in a2xx_gpu_state_get()
[all...]
H A Da4xx_gpu.c277 val = gpu_read(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ); in a4xx_hw_init()
358 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a4xx_recover()
366 gpu_read(gpu, REG_A4XX_RBBM_SW_RESET_CMD); in a4xx_recover()
392 if (spin_until(!(gpu_read(gpu, REG_A4XX_RBBM_STATUS) & in a4xx_idle()
406 status = gpu_read(gpu, REG_A4XX_RBBM_INT_0_STATUS); in a4xx_irq()
410 uint32_t reg = gpu_read(gpu, REG_A4XX_CP_PROTECT_STATUS); in a4xx_irq()
560 state->rbbm_status = gpu_read(gpu, REG_A4XX_RBBM_STATUS); in a4xx_gpu_state_get()
568 gpu_read(gpu, REG_A4XX_RBBM_STATUS)); in a4xx_dump()
586 reg = gpu_read(gpu, REG_A4XX_RBBM_POWER_STATUS); in a4xx_pm_resume()
626 ring->memptrs->rptr = gpu_read(gp in a4xx_get_rptr()
[all...]
H A Da3xx_gpu.c359 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a3xx_recover()
367 gpu_read(gpu, REG_A3XX_RBBM_SW_RESET_CMD); in a3xx_recover()
393 if (spin_until(!(gpu_read(gpu, REG_A3XX_RBBM_STATUS) & in a3xx_idle()
408 status = gpu_read(gpu, REG_A3XX_RBBM_INT_0_STATUS); in a3xx_irq()
462 gpu_read(gpu, REG_A3XX_RBBM_STATUS)); in a3xx_dump()
475 state->rbbm_status = gpu_read(gpu, REG_A3XX_RBBM_STATUS); in a3xx_gpu_state_get()
492 ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR); in a3xx_get_rptr()
H A Da6xx_gpu_state.c177 data[0] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2); in debugbus_read()
178 data[1] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1); in debugbus_read()
220 data[i] = gpu_read(gpu, REG_A6XX_VBIF_TEST_BUS_OUT); in vbif_debugbus_read()
250 clk = gpu_read(gpu, REG_A6XX_VBIF_CLKON); in a6xx_get_vbif_debugbus_block()
770 obj->data[index++] = gpu_read(gpu, in a6xx_get_ahb_gpu_registers()
948 return gpu_read(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2) >> 14; in a6xx_get_cp_roq_size()
972 obj->data[i] = gpu_read(gpu, indexed->data); in a6xx_get_indexed_regs()
994 val = gpu_read(gpu, REG_A6XX_CP_CHICKEN_DBG); in a6xx_get_indexed_registers()
1007 mempool_size = gpu_read(gpu, REG_A6XX_CP_MEM_POOL_SIZE); in a6xx_get_indexed_registers()
1033 bool stalled = !!(gpu_read(gp in a6xx_gpu_state_get()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu.c25 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle()
29 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & in _a6xx_check_idle()
42 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle()
43 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), in a6xx_idle()
44 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), in a6xx_idle()
45 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); in a6xx_idle()
444 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); in a6xx_set_hwcg()
947 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); in a6xx_dump()
964 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i))); in a6xx_recover()
987 gpu_read(gp in a6xx_fault_handler()
[all...]
H A Da5xx_gpu.c849 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(i))); in a5xx_recover()
856 gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD); in a5xx_recover()
896 if (gpu_read(gpu, REG_A5XX_RBBM_STATUS) & ~A5XX_RBBM_STATUS_HI_BUSY) in _a5xx_check_idle()
903 return !(gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS) & in _a5xx_check_idle()
924 gpu_read(gpu, REG_A5XX_RBBM_STATUS), in a5xx_idle()
925 gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS), in a5xx_idle()
926 gpu_read(gpu, REG_A5XX_CP_RB_RPTR), in a5xx_idle()
927 gpu_read(gpu, REG_A5XX_CP_RB_WPTR)); in a5xx_idle()
939 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(4)), in a5xx_fault_handler()
940 gpu_read(gp in a5xx_fault_handler()
[all...]
H A Da5xx_debugfs.c23 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA)); in pfp_print()
36 gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA)); in me_print()
49 gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA)); in meq_print()
64 val[j] = gpu_read(gpu, REG_A5XX_CP_ROQ_DBG_DATA); in roq_print()
H A Da2xx_gpu.c256 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a2xx_recover()
264 gpu_read(gpu, REG_A2XX_RBBM_SOFT_RESET); in a2xx_recover()
288 if (spin_until(!(gpu_read(gpu, REG_A2XX_RBBM_STATUS) & in a2xx_idle()
303 mstatus = gpu_read(gpu, REG_A2XX_MASTER_INT_SIGNAL); in a2xx_irq()
306 status = gpu_read(gpu, REG_A2XX_MH_INTERRUPT_STATUS); in a2xx_irq()
310 gpu_read(gpu, REG_A2XX_MH_MMU_PAGE_FAULT)); in a2xx_irq()
316 status = gpu_read(gpu, REG_AXXX_CP_INT_STATUS); in a2xx_irq()
326 status = gpu_read(gpu, REG_A2XX_RBBM_INT_STATUS); in a2xx_irq()
433 gpu_read(gpu, REG_A2XX_RBBM_STATUS)); in a2xx_dump()
446 state->rbbm_status = gpu_read(gp in a2xx_gpu_state_get()
[all...]
H A Da4xx_gpu.c278 val = gpu_read(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ); in a4xx_hw_init()
359 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a4xx_recover()
367 gpu_read(gpu, REG_A4XX_RBBM_SW_RESET_CMD); in a4xx_recover()
393 if (spin_until(!(gpu_read(gpu, REG_A4XX_RBBM_STATUS) & in a4xx_idle()
407 status = gpu_read(gpu, REG_A4XX_RBBM_INT_0_STATUS); in a4xx_irq()
411 uint32_t reg = gpu_read(gpu, REG_A4XX_CP_PROTECT_STATUS); in a4xx_irq()
561 state->rbbm_status = gpu_read(gpu, REG_A4XX_RBBM_STATUS); in a4xx_gpu_state_get()
569 gpu_read(gpu, REG_A4XX_RBBM_STATUS)); in a4xx_dump()
587 reg = gpu_read(gpu, REG_A4XX_RBBM_POWER_STATUS); in a4xx_pm_resume()
618 ring->memptrs->rptr = gpu_read(gp in a4xx_get_rptr()
[all...]
H A Da3xx_gpu.c360 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a3xx_recover()
368 gpu_read(gpu, REG_A3XX_RBBM_SW_RESET_CMD); in a3xx_recover()
394 if (spin_until(!(gpu_read(gpu, REG_A3XX_RBBM_STATUS) & in a3xx_idle()
409 status = gpu_read(gpu, REG_A3XX_RBBM_INT_0_STATUS); in a3xx_irq()
463 gpu_read(gpu, REG_A3XX_RBBM_STATUS)); in a3xx_dump()
476 state->rbbm_status = gpu_read(gpu, REG_A3XX_RBBM_STATUS); in a3xx_gpu_state_get()
483 ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR); in a3xx_get_rptr()
H A Da6xx_gpu_state.c170 data[0] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2); in debugbus_read()
171 data[1] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1); in debugbus_read()
213 data[i] = gpu_read(gpu, REG_A6XX_VBIF_TEST_BUS_OUT); in vbif_debugbus_read()
243 clk = gpu_read(gpu, REG_A6XX_VBIF_CLKON); in a6xx_get_vbif_debugbus_block()
730 obj->data[index++] = gpu_read(gpu, in a6xx_get_ahb_gpu_registers()
867 obj->data[i] = gpu_read(gpu, indexed->data); in a6xx_get_indexed_regs()
887 mempool_size = gpu_read(gpu, REG_A6XX_CP_MEM_POOL_SIZE); in a6xx_get_indexed_registers()
H A Da5xx_gpu.h143 if ((gpu_read(gpu, reg) & mask) == value) in spin_usecs()
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/
H A Dmsm_gpu.h242 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) in gpu_read() function
249 uint32_t val = gpu_read(gpu, reg); in gpu_rmw()

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