| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | dpp.h | 32 struct dpp { struct
126 struct dpp *dpp_base, const struct pwl_params *params);
128 void (*dpp_set_pre_degam)(struct dpp *dpp_base,
132 void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,
136 struct dpp *dpp_base,
139 void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s);
141 void (*dpp_reset)(struct dpp *dpp);
143 void (*dpp_set_scaler)(struct dpp *dp
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | dpp.h | 44 struct dpp { struct
162 struct dpp *dpp_base, const struct pwl_params *params);
164 void (*dpp_set_pre_degam)(struct dpp *dpp_base,
167 void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,
171 struct dpp *dpp_base,
174 void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s);
176 void (*dpp_reset)(struct dpp *dpp);
178 void (*dpp_set_scaler)(struct dpp *dp
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_dpp_cm.c | 43 dpp->tf_regs->reg
46 dpp->base.ctx
50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
92 struct dcn10_dpp *dpp, in program_gamut_remap()
118 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
120 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
129 dpp in program_gamut_remap()
91 program_gamut_remap( struct dcn10_dpp *dpp, const uint16_t *regval, enum gamut_remap_select select) program_gamut_remap() argument
164 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cm_set_gamut_remap() local
184 dpp1_cm_program_color_matrix( struct dcn10_dpp *dpp, const uint16_t *regval) dpp1_cm_program_color_matrix() argument
243 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cm_set_output_csc_default() local
256 dpp1_cm_get_reg_field( struct dcn10_dpp *dpp, struct xfer_func_reg *reg) dpp1_cm_get_reg_field() argument
283 dpp1_cm_get_degamma_reg_field( struct dcn10_dpp *dpp, struct xfer_func_reg *reg) dpp1_cm_get_degamma_reg_field() argument
313 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cm_set_output_csc_adjustment() local
321 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cm_power_on_regamma_lut() local
333 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cm_program_regamma_lut() local
354 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cm_configure_regamma_lut() local
368 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cm_program_regamma_luta_settings() local
397 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cm_program_regamma_lutb_settings() local
426 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_program_input_csc() local
500 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_program_bias_and_scale() local
521 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_program_degamma_lutb_settings() local
550 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_program_degamma_luta_settings() local
577 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_power_on_degamma_lut() local
587 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_enable_cm_block() local
597 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_set_degamma() local
627 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_degamma_ram_select() local
642 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_degamma_ram_inuse() local
665 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_program_degamma_lut() local
707 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_full_bypass() local
734 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_ingamma_ram_inuse() local
765 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_program_input_lut() local
813 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_set_hdr_multiplier() local
[all...] |
| H A D | dcn10_dpp.c | 42 dpp->tf_regs->reg
45 dpp->base.ctx
49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
94 void dpp_read_state(struct dpp *dpp_base, in dpp_read_state()
97 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp_read_state() local
123 void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp) in dpp_set_gamut_remap_bypass() argument
133 struct dpp *dpp, in dpp1_get_optimal_number_of_taps()
139 dpp in dpp1_get_optimal_number_of_taps()
132 dpp1_get_optimal_number_of_taps( struct dpp *dpp, struct scaler_data *scl_data, const struct scaling_taps *in_taps) dpp1_get_optimal_number_of_taps() argument
198 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_reset() local
214 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cm_set_regamma_pwl() local
270 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_set_degamma_format_float() local
295 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cnv_setup() local
421 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_set_cursor_attributes() local
444 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_set_cursor_position() local
483 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cnv_set_optional_cursor_attributes() local
496 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_dppclk_control() local
548 dpp1_construct( struct dcn10_dpp *dpp, struct dc_context *ctx, uint32_t inst, const struct dcn_dpp_registers *tf_regs, const struct dcn_dpp_shift *tf_shift, const struct dcn_dpp_mask *tf_mask) dpp1_construct() argument
[all...] |
| H A D | dcn10_dpp_dscl.c | 43 dpp->tf_regs->reg
46 dpp->base.ctx
50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
89 struct dcn10_dpp *dpp, in dpp1_dscl_set_overscan()
117 struct dcn10_dpp *dpp, const struct scaler_data *data) in dpp1_dscl_set_otg_blank()
168 struct dpp *dpp_base, in dpp1_dscl_get_dscl_mode()
202 struct dcn10_dpp *dpp, in dpp1_dscl_set_lb()
207 if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { in dpp1_dscl_set_lb()
259 struct dcn10_dpp *dpp, in dpp1_dscl_set_scaler_filter()
88 dpp1_dscl_set_overscan( struct dcn10_dpp *dpp, const struct scaler_data *data) dpp1_dscl_set_overscan() argument
116 dpp1_dscl_set_otg_blank( struct dcn10_dpp *dpp, const struct scaler_data *data) dpp1_dscl_set_otg_blank() argument
201 dpp1_dscl_set_lb( struct dcn10_dpp *dpp, const struct line_buffer_params *lb_params, enum lb_memory_config mem_size_config) dpp1_dscl_set_lb() argument
258 dpp1_dscl_set_scaler_filter( struct dcn10_dpp *dpp, uint32_t taps, enum dcn10_coef_filter_type_sel filter_type, const uint16_t *filter) dpp1_dscl_set_scaler_filter() argument
296 dpp1_dscl_set_scl_filter( struct dcn10_dpp *dpp, const struct scaler_data *scl_data, bool chroma_coef_mode) dpp1_dscl_set_scl_filter() argument
477 dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *dpp, const struct scaler_data *scl_data) dpp1_dscl_find_lb_memory_config() argument
532 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_dscl_set_scaler_auto_scale() local
580 dpp1_dscl_set_manual_ratio_init( struct dcn10_dpp *dpp, const struct scaler_data *data) dpp1_dscl_set_manual_ratio_init() argument
644 dpp1_dscl_set_recout( struct dcn10_dpp *dpp, const struct rect *recout) dpp1_dscl_set_recout() argument
671 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_dscl_set_scaler_manual_scale() local
[all...] |
| H A D | dcn10_hw_sequencer.c | 287 struct dpp *dpp = pool->dpps[i]; in dcn10_log_hw_state() local
290 dpp->funcs->dpp_read_state(dpp, &s); in dcn10_log_hw_state()
297 dpp->inst, in dcn10_log_hw_state()
1051 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn10_plane_atomic_disconnect()
1078 struct dpp *dpp, in dcn10_plane_atomic_power_down()
1089 hws->funcs.dpp_pg_control(hws, dpp->inst, false); in dcn10_plane_atomic_power_down()
1094 dpp in dcn10_plane_atomic_power_down()
1077 dcn10_plane_atomic_power_down(struct dc *dc, struct dpp *dpp, struct hubp *hubp) dcn10_plane_atomic_power_down() argument
1109 struct dpp *dpp = pipe_ctx->plane_res.dpp; dcn10_plane_atomic_disable() local
1208 struct dpp *dpp = dc->res_pool->dpps[i]; dcn10_init_pipes() local
1670 struct dpp *dpp = pipe_ctx->plane_res.dpp; dcn10_set_output_transfer_func() local
2349 dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state) dcn10_update_dpp() argument
2475 struct dpp *dpp = pipe_ctx->plane_res.dpp; dcn10_update_dchubp_dpp() local
3385 struct dpp *dpp = pipe_ctx->plane_res.dpp; dcn10_set_cursor_position() local
[all...] |
| H A D | dcn10_resource.c | 635 static void dcn10_dpp_destroy(struct dpp **dpp) in dcn10_dpp_destroy() argument
637 kfree(TO_DCN10_DPP(*dpp)); in dcn10_dpp_destroy()
638 *dpp = NULL; in dcn10_dpp_destroy()
641 static struct dpp *dcn10_dpp_create( in dcn10_dpp_create()
645 struct dcn10_dpp *dpp = in dcn10_dpp_create() local
648 if (!dpp) in dcn10_dpp_create()
651 dpp1_construct(dpp, ctx, inst, in dcn10_dpp_create()
653 return &dpp->base; in dcn10_dpp_create()
1174 idle_pipe->plane_res.dpp in dcn10_acquire_idle_pipe_for_layer()
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_dpp_cm.c | 43 dpp->tf_regs->reg
46 dpp->base.ctx
50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
92 struct dcn10_dpp *dpp, in program_gamut_remap()
118 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
120 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
129 dpp in program_gamut_remap()
91 program_gamut_remap( struct dcn10_dpp *dpp, const uint16_t *regval, enum gamut_remap_select select) program_gamut_remap() argument
164 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cm_set_gamut_remap() local
184 dpp1_cm_program_color_matrix( struct dcn10_dpp *dpp, const uint16_t *regval) dpp1_cm_program_color_matrix() argument
243 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cm_set_output_csc_default() local
256 dpp1_cm_get_reg_field( struct dcn10_dpp *dpp, struct xfer_func_reg *reg) dpp1_cm_get_reg_field() argument
283 dpp1_cm_get_degamma_reg_field( struct dcn10_dpp *dpp, struct xfer_func_reg *reg) dpp1_cm_get_degamma_reg_field() argument
313 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cm_set_output_csc_adjustment() local
321 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cm_power_on_regamma_lut() local
333 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cm_program_regamma_lut() local
354 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cm_configure_regamma_lut() local
368 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cm_program_regamma_luta_settings() local
397 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cm_program_regamma_lutb_settings() local
426 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_program_input_csc() local
500 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_program_bias_and_scale() local
521 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_program_degamma_lutb_settings() local
550 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_program_degamma_luta_settings() local
577 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_power_on_degamma_lut() local
587 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_enable_cm_block() local
597 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_set_degamma() local
627 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_degamma_ram_select() local
642 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_degamma_ram_inuse() local
665 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_program_degamma_lut() local
707 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_full_bypass() local
734 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_ingamma_ram_inuse() local
765 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_program_input_lut() local
813 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_set_hdr_multiplier() local
[all...] |
| H A D | dcn10_dpp.c | 42 dpp->tf_regs->reg
45 dpp->base.ctx
49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
94 void dpp_read_state(struct dpp *dpp_base, in dpp_read_state()
97 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp_read_state() local
125 struct dpp *dpp, in dpp1_get_optimal_number_of_taps()
131 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT && in dpp1_get_optimal_number_of_taps()
137 dpp in dpp1_get_optimal_number_of_taps()
124 dpp1_get_optimal_number_of_taps( struct dpp *dpp, struct scaler_data *scl_data, const struct scaling_taps *in_taps) dpp1_get_optimal_number_of_taps() argument
190 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp_reset() local
206 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cm_set_regamma_pwl() local
263 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_set_degamma_format_float() local
288 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cnv_setup() local
415 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_set_cursor_attributes() local
438 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_set_cursor_position() local
493 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_cnv_set_optional_cursor_attributes() local
506 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_dppclk_control() local
558 dpp1_construct( struct dcn10_dpp *dpp, struct dc_context *ctx, uint32_t inst, const struct dcn_dpp_registers *tf_regs, const struct dcn_dpp_shift *tf_shift, const struct dcn_dpp_mask *tf_mask) dpp1_construct() argument
[all...] |
| H A D | dcn10_dpp_dscl.c | 44 dpp->tf_regs->reg
47 dpp->base.ctx
51 dpp->tf_shift->field_name, dpp->tf_mask->field_name
124 struct dpp *dpp_base, in dpp1_dscl_get_dscl_mode()
158 struct dpp *dpp_base, in dpp1_power_on_dscl()
161 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_power_on_dscl() local
163 if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) { in dpp1_power_on_dscl()
168 if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) { in dpp1_power_on_dscl()
169 dpp in dpp1_power_on_dscl()
179 dpp1_dscl_set_lb( struct dcn10_dpp *dpp, const struct line_buffer_params *lb_params, enum lb_memory_config mem_size_config) dpp1_dscl_set_lb() argument
240 dpp1_dscl_set_scaler_filter( struct dcn10_dpp *dpp, uint32_t taps, enum dcn10_coef_filter_type_sel filter_type, const uint16_t *filter) dpp1_dscl_set_scaler_filter() argument
278 dpp1_dscl_set_scl_filter( struct dcn10_dpp *dpp, const struct scaler_data *scl_data, bool chroma_coef_mode) dpp1_dscl_set_scl_filter() argument
459 dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *dpp, const struct scaler_data *scl_data) dpp1_dscl_find_lb_memory_config() argument
510 dpp1_dscl_set_manual_ratio_init( struct dcn10_dpp *dpp, const struct scaler_data *data) dpp1_dscl_set_manual_ratio_init() argument
587 dpp1_dscl_set_recout(struct dcn10_dpp *dpp, const struct rect *recout) dpp1_dscl_set_recout() argument
617 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); dpp1_dscl_set_scaler_manual_scale() local
[all...] |
| H A D | dcn10_resource.c | 570 static void dcn10_dpp_destroy(struct dpp **dpp) in dcn10_dpp_destroy() argument
572 kfree(TO_DCN10_DPP(*dpp)); in dcn10_dpp_destroy()
573 *dpp = NULL; in dcn10_dpp_destroy()
576 static struct dpp *dcn10_dpp_create( in dcn10_dpp_create()
580 struct dcn10_dpp *dpp = in dcn10_dpp_create() local
583 if (!dpp) in dcn10_dpp_create()
586 dpp1_construct(dpp, ctx, inst, in dcn10_dpp_create()
588 return &dpp->base; in dcn10_dpp_create()
1111 idle_pipe->plane_res.dpp in dcn10_acquire_free_pipe_for_layer()
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_dpp_cm.c | 34 dpp->tf_regs->reg
37 dpp->base.ctx
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
44 struct dpp *dpp_base) in dpp3_enable_cm_block()
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_enable_cm_block() local
57 static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base) in dpp30_get_gamcor_current()
62 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_get_gamcor_current() local
84 struct dpp *dpp_base, in dpp3_program_gammcor_lut()
90 struct dcn3_dpp *dpp in dpp3_program_gammcor_lut() local
137 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_power_on_gamcor_lut() local
154 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_cm_dealpha() local
165 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_cm_bias() local
173 dpp3_gamcor_reg_field( struct dcn3_dpp *dpp, struct dcn3_xfer_func_reg *reg) dpp3_gamcor_reg_field() argument
210 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_configure_gamcor_lut() local
225 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_gamcor_lut() local
311 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_set_hdr_multiplier() local
317 program_gamut_remap( struct dcn3_dpp *dpp, const uint16_t *regval, int select) program_gamut_remap() argument
380 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_cm_set_gamut_remap() local
[all...] |
| H A D | dcn30_dpp.c | 34 dpp->tf_regs->reg
37 dpp->base.ctx
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
44 void dpp30_read_state(struct dpp *dpp_base, in dpp30_read_state()
47 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp30_read_state() local
54 /*program post scaler scs block in dpp CM*/
56 struct dpp *dpp_base, in dpp3_program_post_csc()
61 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_post_csc() local
101 gam_regs.shifts.csc_c11 = dpp in dpp3_program_post_csc()
131 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_set_pre_degam() local
179 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_cnv_setup() local
353 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_set_cursor_attributes() local
378 dpp3_get_optimal_number_of_taps( struct dpp *dpp, struct scaler_data *scl_data, const struct scaling_taps *in_taps) dpp3_get_optimal_number_of_taps() argument
490 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_cnv_set_bias_scale() local
504 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_power_on_blnd_lut() local
515 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_configure_blnd_lut() local
530 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_blnd_pwl() local
557 dcn3_dpp_cm_get_reg_field( struct dcn3_dpp *dpp, struct dcn3_xfer_func_reg *reg) dcn3_dpp_cm_get_reg_field() argument
589 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_blnd_luta_settings() local
617 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_blnd_lutb_settings() local
646 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_get_blndgam_current() local
677 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_blnd_lut() local
718 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_shaper_lut() local
745 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_get_shaper_current() local
771 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_configure_shaper_lut() local
787 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_shaper_luta_settings() local
937 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_shaper_lutb_settings() local
1090 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_shaper() local
1126 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); get3dlut_config() local
1173 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_set_3dlut_mode() local
1192 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_select_3dlut_ram() local
1208 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_set3dlut_ram12() local
1242 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_set3dlut_ram10() local
1261 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_select_3dlut_ram_mask() local
1389 dpp3_construct( struct dcn3_dpp *dpp, struct dc_context *ctx, uint32_t inst, const struct dcn3_dpp_registers *tf_regs, const struct dcn3_dpp_shift *tf_shift, const struct dcn3_dpp_mask *tf_mask) dpp3_construct() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_dpp_cm.c | 34 dpp->tf_regs->reg
37 dpp->base.ctx
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
44 struct dpp *dpp_base) in dpp3_enable_cm_block()
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_enable_cm_block() local
57 static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base) in dpp30_get_gamcor_current()
62 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_get_gamcor_current() local
81 struct dpp *dpp_base, in dpp3_program_gammcor_lut()
87 struct dcn3_dpp *dpp in dpp3_program_gammcor_lut() local
133 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_power_on_gamcor_lut() local
152 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_cm_dealpha() local
163 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_cm_bias() local
171 dpp3_gamcor_reg_field( struct dcn3_dpp *dpp, struct dcn3_xfer_func_reg *reg) dpp3_gamcor_reg_field() argument
208 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_configure_gamcor_lut() local
223 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_gamcor_lut() local
311 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_set_hdr_multiplier() local
317 program_gamut_remap( struct dcn3_dpp *dpp, const uint16_t *regval, int select) program_gamut_remap() argument
380 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_cm_set_gamut_remap() local
[all...] |
| H A D | dcn30_dpp.c | 34 dpp->tf_regs->reg
37 dpp->base.ctx
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
44 void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) in dpp30_read_state()
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_read_state() local
53 /*program post scaler scs block in dpp CM*/
55 struct dpp *dpp_base, in dpp3_program_post_csc()
60 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_post_csc() local
100 gam_regs.shifts.csc_c11 = dpp in dpp3_program_post_csc()
130 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_set_pre_degam() local
178 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_cnv_setup() local
356 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_set_cursor_attributes() local
385 dpp3_get_optimal_number_of_taps( struct dpp *dpp, struct scaler_data *scl_data, const struct scaling_taps *in_taps) dpp3_get_optimal_number_of_taps() argument
489 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_deferred_update() local
537 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_power_on_blnd_lut() local
557 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_power_on_hdr3dlut() local
574 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_power_on_shaper() local
591 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_configure_blnd_lut() local
606 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_blnd_pwl() local
633 dcn3_dpp_cm_get_reg_field( struct dcn3_dpp *dpp, struct dcn3_xfer_func_reg *reg) dcn3_dpp_cm_get_reg_field() argument
665 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_blnd_luta_settings() local
693 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_blnd_lutb_settings() local
722 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_get_blndgam_current() local
752 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_blnd_lut() local
795 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_shaper_lut() local
822 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_get_shaper_current() local
848 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_configure_shaper_lut() local
864 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_shaper_luta_settings() local
1014 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_shaper_lutb_settings() local
1166 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_program_shaper() local
1208 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); get3dlut_config() local
1255 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_set_3dlut_mode() local
1274 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_select_3dlut_ram() local
1290 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_set3dlut_ram12() local
1324 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_set3dlut_ram10() local
1343 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); dpp3_select_3dlut_ram_mask() local
1470 dpp3_construct( struct dcn3_dpp *dpp, struct dc_context *ctx, uint32_t inst, const struct dcn3_dpp_registers *tf_regs, const struct dcn3_dpp_shift *tf_shift, const struct dcn3_dpp_mask *tf_mask) dpp3_construct() argument
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_dpp_cm.c | 37 dpp->tf_regs->reg
43 dpp->base.ctx
47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
51 struct dpp *dpp_base) in dpp2_enable_cm_block()
53 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_enable_cm_block() local
65 struct dpp *dpp_base, in dpp2_degamma_ram_inuse()
70 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_degamma_ram_inuse() local
86 struct dpp *dpp_base, in dpp2_program_degamma_lut()
93 struct dcn20_dpp *dpp in dpp2_program_degamma_lut() local
138 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_set_degamma() local
161 program_gamut_remap( struct dcn20_dpp *dpp, const uint16_t *regval, enum dcn20_gamut_remap_select select) program_gamut_remap() argument
217 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_cm_set_gamut_remap() local
243 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_program_input_csc() local
314 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_power_on_blnd_lut() local
325 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_configure_blnd_lut() local
340 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_blnd_pwl() local
358 dcn20_dpp_cm_get_reg_field( struct dcn20_dpp *dpp, struct xfer_func_reg *reg) dcn20_dpp_cm_get_reg_field() argument
390 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_blnd_luta_settings() local
418 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_blnd_lutb_settings() local
445 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_get_blndgam_current() local
472 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_blnd_lut() local
511 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_shaper_lut() local
538 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_get_shaper_current() local
564 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_configure_shaper_lut() local
580 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_shaper_luta_settings() local
730 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_shaper_lutb_settings() local
883 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_shaper() local
919 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); get3dlut_config() local
965 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_set_3dlut_mode() local
984 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_select_3dlut_ram() local
1000 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_set3dlut_ram12() local
1034 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_set3dlut_ram10() local
1053 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_select_3dlut_ram_mask() local
1144 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_set_hdr_multiplier() local
[all...] |
| H A D | dcn20_dpp.c | 42 dpp->tf_regs->reg
45 dpp->base.ctx
49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
51 void dpp20_read_state(struct dpp *dpp_base, in dpp20_read_state()
54 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp20_read_state() local
76 struct dpp *dpp_base, in dpp2_power_on_obuf()
79 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_power_on_obuf() local
91 struct dpp *dpp_base, in dpp2_dummy_program_input_lut()
96 struct dpp *dpp_bas in dpp2_cnv_setup()
103 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_cnv_setup() local
257 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_cnv_set_bias_scale() local
328 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_cnv_set_alpha_keyer() local
352 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_set_cursor_attributes() local
376 oppn20_dummy_program_regamma_pwl( struct dpp *dpp, const struct pwl_params *params, enum opp_regamma mode) oppn20_dummy_program_regamma_pwl() argument
413 dpp2_construct( struct dcn20_dpp *dpp, struct dc_context *ctx, uint32_t inst, const struct dcn2_dpp_registers *tf_regs, const struct dcn2_dpp_shift *tf_shift, const struct dcn2_dpp_mask *tf_mask) dpp2_construct() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_dpp_cm.c | 37 dpp->tf_regs->reg
43 dpp->base.ctx
47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
51 struct dpp *dpp_base) in dpp2_enable_cm_block()
53 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_enable_cm_block() local
65 struct dpp *dpp_base, in dpp2_degamma_ram_inuse()
70 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_degamma_ram_inuse() local
86 struct dpp *dpp_base, in dpp2_program_degamma_lut()
93 struct dcn20_dpp *dpp in dpp2_program_degamma_lut() local
138 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_set_degamma() local
161 program_gamut_remap( struct dcn20_dpp *dpp, const uint16_t *regval, enum dcn20_gamut_remap_select select) program_gamut_remap() argument
217 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_cm_set_gamut_remap() local
243 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_program_input_csc() local
314 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_power_on_blnd_lut() local
325 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_configure_blnd_lut() local
340 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_blnd_pwl() local
358 dcn20_dpp_cm_get_reg_field( struct dcn20_dpp *dpp, struct xfer_func_reg *reg) dcn20_dpp_cm_get_reg_field() argument
390 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_blnd_luta_settings() local
418 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_blnd_lutb_settings() local
445 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_get_blndgam_current() local
472 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_blnd_lut() local
511 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_shaper_lut() local
538 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_get_shaper_current() local
564 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_configure_shaper_lut() local
580 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_shaper_luta_settings() local
730 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_shaper_lutb_settings() local
883 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_program_shaper() local
919 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); get3dlut_config() local
965 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_set_3dlut_mode() local
984 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_select_3dlut_ram() local
1000 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_set3dlut_ram12() local
1034 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_set3dlut_ram10() local
1053 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp20_select_3dlut_ram_mask() local
1144 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_set_hdr_multiplier() local
[all...] |
| H A D | dcn20_dpp.c | 42 dpp->tf_regs->reg
45 dpp->base.ctx
49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
51 void dpp20_read_state(struct dpp *dpp_base, in dpp20_read_state()
54 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp20_read_state() local
76 struct dpp *dpp_base, in dpp2_power_on_obuf()
79 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_power_on_obuf() local
91 struct dpp *dpp_base, in dpp2_dummy_program_input_lut()
96 struct dpp *dpp_bas in dpp2_cnv_setup()
103 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_cnv_setup() local
318 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_cnv_set_alpha_keyer() local
342 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); dpp2_set_cursor_attributes() local
366 oppn20_dummy_program_regamma_pwl( struct dpp *dpp, const struct pwl_params *params, enum opp_regamma mode) oppn20_dummy_program_regamma_pwl() argument
403 dpp2_construct( struct dcn20_dpp *dpp, struct dc_context *ctx, uint32_t inst, const struct dcn2_dpp_registers *tf_regs, const struct dcn2_dpp_shift *tf_shift, const struct dcn2_dpp_mask *tf_mask) dpp2_construct() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_dpp.c | 35 dpp->tf_regs->reg
38 dpp->base.ctx
42 dpp->tf_shift->field_name, dpp->tf_mask->field_name
45 struct dpp *dpp_base, in dpp201_cnv_setup()
52 struct dcn201_dpp *dpp = TO_DCN201_DPP(dpp_base); in dpp201_cnv_setup() local
184 struct dpp *dpp, in dpp201_get_optimal_number_of_taps()
190 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT && in dpp201_get_optimal_number_of_taps()
195 dpp in dpp201_get_optimal_number_of_taps()
183 dpp201_get_optimal_number_of_taps( struct dpp *dpp, struct scaler_data *scl_data, const struct scaling_taps *in_taps) dpp201_get_optimal_number_of_taps() argument
285 dpp201_construct( struct dcn201_dpp *dpp, struct dc_context *ctx, uint32_t inst, const struct dcn201_dpp_registers *tf_regs, const struct dcn201_dpp_shift *tf_shift, const struct dcn201_dpp_mask *tf_mask) dpp201_construct() argument
[all...] |
| H A D | dcn201_resource.c | 619 static void dcn201_dpp_destroy(struct dpp **dpp) in dcn201_dpp_destroy() argument
621 kfree(TO_DCN201_DPP(*dpp)); in dcn201_dpp_destroy()
622 *dpp = NULL; in dcn201_dpp_destroy()
625 static struct dpp *dcn201_dpp_create( in dcn201_dpp_create()
629 struct dcn201_dpp *dpp = in dcn201_dpp_create() local
632 if (!dpp) in dcn201_dpp_create()
635 if (dpp201_construct(dpp, ctx, inst, in dcn201_dpp_create()
637 return &dpp->base; in dcn201_dpp_create()
639 kfree(dpp); in dcn201_dpp_create()
[all...] |
| H A D | dcn201_dpp.h | 30 #define TO_DCN201_DPP(dpp)\
31 container_of(dpp, struct dcn201_dpp, base)
58 struct dpp base;
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_dpp.c | 146 struct dcn3_dpp *dpp, in dpp32_construct()
153 dpp->base.ctx = ctx; in dpp32_construct()
155 dpp->base.inst = inst; in dpp32_construct()
156 dpp->base.funcs = &dcn32_dpp_funcs; in dpp32_construct()
157 dpp->base.caps = &dcn32_dpp_cap; in dpp32_construct()
159 dpp->tf_regs = tf_regs; in dpp32_construct()
160 dpp->tf_shift = tf_shift; in dpp32_construct()
161 dpp->tf_mask = tf_mask; in dpp32_construct()
145 dpp32_construct( struct dcn3_dpp *dpp, struct dc_context *ctx, uint32_t inst, const struct dcn3_dpp_registers *tf_regs, const struct dcn3_dpp_shift *tf_shift, const struct dcn3_dpp_mask *tf_mask) dpp32_construct() argument
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn302/ |
| H A D | dcn302_resource.c | 535 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn302_dpp_create()
537 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); in dcn302_dpp_create() local
539 if (!dpp) in dcn302_dpp_create()
542 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn302_dpp_create()
543 return &dpp->base; in dcn302_dpp_create()
546 kfree(dpp); in dcn302_dpp_create()
1235 dc->caps.color.dpp.dcn_arch = 1; in dcn302_resource_construct()
1236 dc->caps.color.dpp.input_lut_shared = 0; in dcn302_resource_construct()
1237 dc->caps.color.dpp.icsc = 1; in dcn302_resource_construct()
1238 dc->caps.color.dpp in dcn302_resource_construct()
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn303/ |
| H A D | dcn303_resource.c | 495 static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn303_dpp_create()
497 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); in dcn303_dpp_create() local
499 if (!dpp) in dcn303_dpp_create()
502 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn303_dpp_create()
503 return &dpp->base; in dcn303_dpp_create()
506 kfree(dpp); in dcn303_dpp_create()
1159 dc->caps.color.dpp.dcn_arch = 1; in dcn303_resource_construct()
1160 dc->caps.color.dpp.input_lut_shared = 0; in dcn303_resource_construct()
1161 dc->caps.color.dpp.icsc = 1; in dcn303_resource_construct()
1162 dc->caps.color.dpp in dcn303_resource_construct()
[all...] |