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/kernel/linux/linux-5.10/arch/sh/lib/
H A Dudivsi3_i4i-Os.S38 div1 r5,r4
40 div1 r5,r4
41 div1 r5,r4
43 div1 r5,r4
48 div1 r5,r4
50 div1 r5,r4
58 div1 r5,r4
60 div1 r5,r4; div1 r5,r4; div1 r
[all...]
H A Dudivsi3.S16 div1 r5,r4
18 div1 r5,r4; div1 r5,r4; div1 r5,r4
19 div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
22 div1 r5,r4; rotcl r0
23 div1 r
[all...]
H A Dudivsi3_i4i.S24 div1 with case distinction for larger divisors in three more ranges.
55 div1 r5,r0
57 div1 r5,r0
58 div1 r5,r0
60 div1 r5,r0
102 div1 r5,r0
109 div1 r5,r0
112 div1 r5,r0
115 div1 r5,r0
118 div1 r
[all...]
/kernel/linux/linux-6.6/arch/sh/lib/
H A Dudivsi3_i4i-Os.S38 div1 r5,r4
40 div1 r5,r4
41 div1 r5,r4
43 div1 r5,r4
48 div1 r5,r4
50 div1 r5,r4
58 div1 r5,r4
60 div1 r5,r4; div1 r5,r4; div1 r
[all...]
H A Dudivsi3.S16 div1 r5,r4
18 div1 r5,r4; div1 r5,r4; div1 r5,r4
19 div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
22 div1 r5,r4; rotcl r0
23 div1 r
[all...]
H A Dudivsi3_i4i.S24 div1 with case distinction for larger divisors in three more ranges.
55 div1 r5,r0
57 div1 r5,r0
58 div1 r5,r0
60 div1 r5,r0
102 div1 r5,r0
109 div1 r5,r0
112 div1 r5,r0
115 div1 r5,r0
118 div1 r
[all...]
/kernel/linux/linux-5.10/drivers/clk/
H A Dclk-vt8500.c456 int div1, div2; in wm8750_find_pll_bits() local
462 for (div1 = 1; div1 >= 0; div1--) in wm8750_find_pll_bits()
465 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2)); in wm8750_find_pll_bits()
471 *filter = wm8750_get_filter(parent_rate, div1); in wm8750_find_pll_bits()
473 *divisor1 = div1; in wm8750_find_pll_bits()
481 *divisor1 = div1; in wm8750_find_pll_bits()
504 int div1, div2; in wm8850_find_pll_bits() local
510 for (div1 in wm8850_find_pll_bits()
550 u32 filter, mul, div1, div2; vtwm_pll_set_rate() local
601 u32 filter, mul, div1, div2; vtwm_pll_round_rate() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/
H A Dclk-vt8500.c456 int div1, div2; in wm8750_find_pll_bits() local
462 for (div1 = 1; div1 >= 0; div1--) in wm8750_find_pll_bits()
465 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2)); in wm8750_find_pll_bits()
471 *filter = wm8750_get_filter(parent_rate, div1); in wm8750_find_pll_bits()
473 *divisor1 = div1; in wm8750_find_pll_bits()
481 *divisor1 = div1; in wm8750_find_pll_bits()
504 int div1, div2; in wm8850_find_pll_bits() local
510 for (div1 in wm8850_find_pll_bits()
550 u32 filter, mul, div1, div2; vtwm_pll_set_rate() local
601 u32 filter, mul, div1, div2; vtwm_pll_round_rate() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/uniphier/
H A Dclk-uniphier.h110 #define UNIPHIER_CLK_DIV2(parent, div0, div1) \
112 UNIPHIER_CLK_DIV(parent, div1)
114 #define UNIPHIER_CLK_DIV3(parent, div0, div1, div2) \
115 UNIPHIER_CLK_DIV2(parent, div0, div1), \
118 #define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3) \
119 UNIPHIER_CLK_DIV2(parent, div0, div1), \
122 #define UNIPHIER_CLK_DIV5(parent, div0, div1, div2, div3, div4) \
123 UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3), \
/kernel/linux/linux-5.10/drivers/clk/uniphier/
H A Dclk-uniphier.h110 #define UNIPHIER_CLK_DIV2(parent, div0, div1) \
112 UNIPHIER_CLK_DIV(parent, div1)
114 #define UNIPHIER_CLK_DIV3(parent, div0, div1, div2) \
115 UNIPHIER_CLK_DIV2(parent, div0, div1), \
118 #define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3) \
119 UNIPHIER_CLK_DIV2(parent, div0, div1), \
/kernel/linux/linux-5.10/drivers/clk/imx/
H A Dclk-composite-8m.c54 int div1, div2; in imx8m_clk_composite_compute_dividers() local
61 for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) { in imx8m_clk_composite_compute_dividers()
63 int new_error = ((parent_rate / div1) / div2) - rate; in imx8m_clk_composite_compute_dividers()
66 *prediv = div1; in imx8m_clk_composite_compute_dividers()
/kernel/linux/linux-5.10/drivers/clk/samsung/
H A Dclk-cpu.c155 unsigned long div0, div1 = 0, mux_reg; in exynos_cpuclk_pre_rate_change() local
174 div1 = cfg_data->div1; in exynos_cpuclk_pre_rate_change()
176 div1 = readl(base + E4210_DIV_CPU1) & in exynos_cpuclk_pre_rate_change()
216 writel(div1, base + E4210_DIV_CPU1); in exynos_cpuclk_pre_rate_change()
283 unsigned long div0, div1 = 0, mux_reg; in exynos5433_cpuclk_pre_rate_change() local
300 div1 = cfg_data->div1; in exynos5433_cpuclk_pre_rate_change()
329 writel(div1, base + E5433_DIV_CPU1); in exynos5433_cpuclk_pre_rate_change()
/kernel/linux/linux-6.6/drivers/clk/samsung/
H A Dclk-cpu.c155 unsigned long div0, div1 = 0, mux_reg; in exynos_cpuclk_pre_rate_change() local
174 div1 = cfg_data->div1; in exynos_cpuclk_pre_rate_change()
176 div1 = readl(base + E4210_DIV_CPU1) & in exynos_cpuclk_pre_rate_change()
216 writel(div1, base + E4210_DIV_CPU1); in exynos_cpuclk_pre_rate_change()
283 unsigned long div0, div1 = 0, mux_reg; in exynos5433_cpuclk_pre_rate_change() local
300 div1 = cfg_data->div1; in exynos5433_cpuclk_pre_rate_change()
329 writel(div1, base + E5433_DIV_CPU1); in exynos5433_cpuclk_pre_rate_change()
/kernel/linux/linux-6.6/drivers/clk/imx/
H A Dclk-composite-8m.c54 int div1, div2; in imx8m_clk_composite_compute_dividers() local
61 for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) { in imx8m_clk_composite_compute_dividers()
63 int new_error = ((parent_rate / div1) / div2) - rate; in imx8m_clk_composite_compute_dividers()
66 *prediv = div1; in imx8m_clk_composite_compute_dividers()
/kernel/linux/linux-5.10/drivers/spi/
H A Dspi-omap-uwire.c317 int div1; in uwire_setup_transfer() local
362 div1 = 2; in uwire_setup_transfer()
365 div1 = 4; in uwire_setup_transfer()
368 div1 = 7; in uwire_setup_transfer()
372 div1 = 10; in uwire_setup_transfer()
375 div2 = (rate / div1 + hz - 1) / hz; in uwire_setup_transfer()
392 rate /= div1; in uwire_setup_transfer()
/kernel/linux/linux-6.6/drivers/spi/
H A Dspi-omap-uwire.c314 int div1; in uwire_setup_transfer() local
359 div1 = 2; in uwire_setup_transfer()
362 div1 = 4; in uwire_setup_transfer()
365 div1 = 7; in uwire_setup_transfer()
369 div1 = 10; in uwire_setup_transfer()
372 div2 = (rate / div1 + hz - 1) / hz; in uwire_setup_transfer()
389 rate /= div1; in uwire_setup_transfer()
/kernel/linux/linux-5.10/arch/microblaze/lib/
H A Dudivsi3.S53 div1: label
55 bgtid r5, div1
H A Dmodsi3.S39 div1: label
41 bgeid r5, div1
H A Ddivsi3.S39 div1: label
41 bgtid r5, div1
/kernel/linux/linux-6.6/arch/microblaze/lib/
H A Ddivsi3.S39 div1: label
41 bgtid r5, div1
H A Dudivsi3.S53 div1: label
55 bgtid r5, div1
H A Dmodsi3.S39 div1: label
41 bgeid r5, div1
/kernel/linux/linux-5.10/drivers/media/tuners/
H A Dmt2131.c89 u32 div1, num1, div2, num2; in mt2131_set_params() local
106 div1 = num1 / 8192; in mt2131_set_params()
137 b[3] = div1; in mt2131_set_params()
145 dprintk(1, "PLL div1=%d num1=%d div2=%d num2=%d\n", in mt2131_set_params()
146 (int)div1, (int)num1, (int)div2, (int)num2); in mt2131_set_params()
/kernel/linux/linux-6.6/drivers/media/tuners/
H A Dmt2131.c89 u32 div1, num1, div2, num2; in mt2131_set_params() local
106 div1 = num1 / 8192; in mt2131_set_params()
137 b[3] = div1; in mt2131_set_params()
145 dprintk(1, "PLL div1=%d num1=%d div2=%d num2=%d\n", in mt2131_set_params()
146 (int)div1, (int)num1, (int)div2, (int)num2); in mt2131_set_params()
/kernel/linux/linux-5.10/arch/mips/alchemy/common/
H A Dclock.c379 long div1, div2; in alchemy_calc_div() local
381 div1 = prate / rate; in alchemy_calc_div()
382 if ((prate / div1) > rate) in alchemy_calc_div()
383 div1++; in alchemy_calc_div()
386 if (div1 & 1) in alchemy_calc_div()
387 div1++; /* stay <=prate */ in alchemy_calc_div()
390 div2 = (div1 / scale) - 1; /* value to write to register */ in alchemy_calc_div()
397 div1 = ((div2 + 1) * scale); in alchemy_calc_div()
398 return div1; in alchemy_calc_div()

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