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Searched refs:ctrl_reg (Results 1 - 25 of 150) sorted by relevance

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/kernel/linux/linux-5.10/drivers/rtc/
H A Drtc-pm8xxx.c54 * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
80 unsigned int ctrl_reg, rtc_ctrl_reg; in pm8xxx_rtc_set_time() local
98 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); in pm8xxx_rtc_set_time()
102 if (ctrl_reg & regs->alarm_en) { in pm8xxx_rtc_set_time()
104 ctrl_reg &= ~regs->alarm_en; in pm8xxx_rtc_set_time()
105 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); in pm8xxx_rtc_set_time()
160 ctrl_reg |= regs->alarm_en; in pm8xxx_rtc_set_time()
161 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); in pm8xxx_rtc_set_time()
293 unsigned int ctrl_reg; in pm8xxx_rtc_alarm_irq_enable() local
298 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); in pm8xxx_rtc_alarm_irq_enable()
340 unsigned int ctrl_reg; pm8xxx_alarm_trigger() local
388 unsigned int ctrl_reg; pm8xxx_rtc_enable() local
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/kernel/linux/linux-6.6/drivers/spi/
H A Dspi-cadence.c155 u32 ctrl_reg = 0; in cdns_spi_init_hw() local
158 ctrl_reg |= CDNS_SPI_CR_DEFAULT; in cdns_spi_init_hw()
161 ctrl_reg |= CDNS_SPI_CR_PERI_SEL; in cdns_spi_init_hw()
171 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); in cdns_spi_init_hw()
183 u32 ctrl_reg; in cdns_spi_chipselect() local
185 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); in cdns_spi_chipselect()
189 ctrl_reg |= CDNS_SPI_CR_SSCTRL; in cdns_spi_chipselect()
192 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL; in cdns_spi_chipselect()
194 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) << in cdns_spi_chipselect()
198 ctrl_reg | in cdns_spi_chipselect()
214 u32 ctrl_reg, new_ctrl_reg; cdns_spi_config_clock_mode() local
257 u32 ctrl_reg, baud_rate_val; cdns_spi_config_clock_freq() local
491 u32 ctrl_reg; cdns_unprepare_transfer_hardware() local
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H A Dspi-jcore.c44 static int jcore_spi_wait(void __iomem *ctrl_reg) in jcore_spi_wait() argument
49 if (!(readl(ctrl_reg) & JCORE_SPI_STAT_BUSY)) in jcore_spi_wait()
59 void __iomem *ctrl_reg = hw->base + CTRL_REG; in jcore_spi_program() local
61 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_program()
65 writel(hw->cs_reg | hw->speed_reg, ctrl_reg); in jcore_spi_program()
102 void __iomem *ctrl_reg = hw->base + CTRL_REG; in jcore_spi_txrx() local
120 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_txrx()
124 writel(xmit, ctrl_reg); in jcore_spi_txrx()
126 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_txrx()
/kernel/linux/linux-5.10/drivers/clk/microchip/
H A Dclk-core.c91 void __iomem *ctrl_reg; member
101 return readl(pb->ctrl_reg) & PB_DIV_ENABLE; in pbclk_is_enabled()
108 writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg)); in pbclk_enable()
116 writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg)); in pbclk_disable()
147 return ((readl(pb->ctrl_reg) >> PB_DIV_SHIFT) & PB_DIV_MASK) + 1; in pbclk_read_pbdiv()
174 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, in pbclk_set_rate()
185 v = readl(pb->ctrl_reg); in pbclk_set_rate()
191 writel(v, pb->ctrl_reg); in pbclk_set_rate()
196 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, in pbclk_set_rate()
226 pbclk->ctrl_reg in pic32_periph_clk_register()
240 void __iomem *ctrl_reg; global() member
582 void __iomem *ctrl_reg; global() member
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/kernel/linux/linux-6.6/drivers/clk/microchip/
H A Dclk-core.c91 void __iomem *ctrl_reg; member
101 return readl(pb->ctrl_reg) & PB_DIV_ENABLE; in pbclk_is_enabled()
108 writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg)); in pbclk_enable()
116 writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg)); in pbclk_disable()
147 return ((readl(pb->ctrl_reg) >> PB_DIV_SHIFT) & PB_DIV_MASK) + 1; in pbclk_read_pbdiv()
174 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, in pbclk_set_rate()
185 v = readl(pb->ctrl_reg); in pbclk_set_rate()
191 writel(v, pb->ctrl_reg); in pbclk_set_rate()
196 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, in pbclk_set_rate()
226 pbclk->ctrl_reg in pic32_periph_clk_register()
240 void __iomem *ctrl_reg; global() member
582 void __iomem *ctrl_reg; global() member
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/kernel/linux/linux-5.10/drivers/watchdog/
H A Dmachzwd.c187 unsigned int ctrl_reg = 0; in zf_timer_off() local
195 ctrl_reg = zf_get_control(); in zf_timer_off()
196 ctrl_reg |= (ENABLE_WD1|ENABLE_WD2); /* disable wd1 and wd2 */ in zf_timer_off()
197 ctrl_reg &= ~(ENABLE_WD1|ENABLE_WD2); in zf_timer_off()
198 zf_set_control(ctrl_reg); in zf_timer_off()
210 unsigned int ctrl_reg = 0; in zf_timer_on() local
226 ctrl_reg = zf_get_control(); in zf_timer_on()
227 ctrl_reg |= (ENABLE_WD1|zf_action); in zf_timer_on()
228 zf_set_control(ctrl_reg); in zf_timer_on()
237 unsigned int ctrl_reg in zf_ping() local
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/kernel/linux/linux-6.6/drivers/watchdog/
H A Dmachzwd.c188 unsigned int ctrl_reg = 0; in zf_timer_off() local
196 ctrl_reg = zf_get_control(); in zf_timer_off()
197 ctrl_reg |= (ENABLE_WD1|ENABLE_WD2); /* disable wd1 and wd2 */ in zf_timer_off()
198 ctrl_reg &= ~(ENABLE_WD1|ENABLE_WD2); in zf_timer_off()
199 zf_set_control(ctrl_reg); in zf_timer_off()
211 unsigned int ctrl_reg = 0; in zf_timer_on() local
227 ctrl_reg = zf_get_control(); in zf_timer_on()
228 ctrl_reg |= (ENABLE_WD1|zf_action); in zf_timer_on()
229 zf_set_control(ctrl_reg); in zf_timer_on()
238 unsigned int ctrl_reg in zf_ping() local
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/kernel/linux/linux-5.10/drivers/bluetooth/
H A Dbluecard_cs.c79 unsigned char ctrl_reg; member
265 info->ctrl_reg |= REG_CONTROL_RTS; in bluecard_write_wakeup()
266 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
307 info->ctrl_reg &= ~0x03; in bluecard_write_wakeup()
308 info->ctrl_reg |= baud_reg; in bluecard_write_wakeup()
309 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
312 info->ctrl_reg &= ~REG_CONTROL_RTS; in bluecard_write_wakeup()
313 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
512 info->ctrl_reg &= ~REG_CONTROL_INTERRUPT; in bluecard_interrupt()
513 outb(info->ctrl_reg, iobas in bluecard_interrupt()
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/kernel/linux/linux-6.6/drivers/bluetooth/
H A Dbluecard_cs.c79 unsigned char ctrl_reg; member
265 info->ctrl_reg |= REG_CONTROL_RTS; in bluecard_write_wakeup()
266 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
307 info->ctrl_reg &= ~0x03; in bluecard_write_wakeup()
308 info->ctrl_reg |= baud_reg; in bluecard_write_wakeup()
309 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
312 info->ctrl_reg &= ~REG_CONTROL_RTS; in bluecard_write_wakeup()
313 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
512 info->ctrl_reg &= ~REG_CONTROL_INTERRUPT; in bluecard_interrupt()
513 outb(info->ctrl_reg, iobas in bluecard_interrupt()
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/kernel/linux/linux-6.6/drivers/ntb/hw/epf/
H A Dntb_hw_epf.c75 void __iomem *ctrl_reg; member
108 writel(argument, ndev->ctrl_reg + NTB_EPF_ARGUMENT); in ntb_epf_send_command()
109 writel(command, ndev->ctrl_reg + NTB_EPF_COMMAND); in ntb_epf_send_command()
114 status = readw(ndev->ctrl_reg + NTB_EPF_CMD_STATUS); in ntb_epf_send_command()
132 writew(0, ndev->ctrl_reg + NTB_EPF_CMD_STATUS); in ntb_epf_send_command()
200 status = readw(ndev->ctrl_reg + NTB_EPF_LINK_STATUS); in ntb_epf_link_is_up()
216 offset = readl(ndev->ctrl_reg + NTB_EPF_SPAD_OFFSET); in ntb_epf_spad_read()
219 return readl(ndev->ctrl_reg + offset); in ntb_epf_spad_read()
234 offset = readl(ndev->ctrl_reg + NTB_EPF_SPAD_OFFSET); in ntb_epf_spad_write()
236 writel(val, ndev->ctrl_reg in ntb_epf_spad_write()
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/kernel/linux/linux-5.10/drivers/pci/hotplug/
H A Dshpchp.h177 struct ctrl_reg { struct
195 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset),
196 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
197 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
198 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
199 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
200 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
201 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
202 CMD = offsetof(struct ctrl_reg, cmd),
203 CMD_STATUS = offsetof(struct ctrl_reg, cmd_statu
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H A Dcpqphp.h108 struct ctrl_reg { /* offset */ struct
140 SLOT_RST = offsetof(struct ctrl_reg, slot_RST),
141 SLOT_ENABLE = offsetof(struct ctrl_reg, slot_enable),
142 MISC = offsetof(struct ctrl_reg, misc),
143 LED_CONTROL = offsetof(struct ctrl_reg, led_control),
144 INT_INPUT_CLEAR = offsetof(struct ctrl_reg, int_input_clear),
145 INT_MASK = offsetof(struct ctrl_reg, int_mask),
146 CTRL_RESERVED0 = offsetof(struct ctrl_reg, reserved0),
147 CTRL_RESERVED1 = offsetof(struct ctrl_reg, reserved1),
148 CTRL_RESERVED2 = offsetof(struct ctrl_reg, reserved
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/kernel/linux/linux-6.6/drivers/pci/hotplug/
H A Dshpchp.h177 struct ctrl_reg { struct
195 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset),
196 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
197 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
198 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
199 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
200 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
201 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
202 CMD = offsetof(struct ctrl_reg, cmd),
203 CMD_STATUS = offsetof(struct ctrl_reg, cmd_statu
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H A Dcpqphp.h108 struct ctrl_reg { /* offset */ struct
140 SLOT_RST = offsetof(struct ctrl_reg, slot_RST),
141 SLOT_ENABLE = offsetof(struct ctrl_reg, slot_enable),
142 MISC = offsetof(struct ctrl_reg, misc),
143 LED_CONTROL = offsetof(struct ctrl_reg, led_control),
144 INT_INPUT_CLEAR = offsetof(struct ctrl_reg, int_input_clear),
145 INT_MASK = offsetof(struct ctrl_reg, int_mask),
146 CTRL_RESERVED0 = offsetof(struct ctrl_reg, reserved0),
147 CTRL_RESERVED1 = offsetof(struct ctrl_reg, reserved1),
148 CTRL_RESERVED2 = offsetof(struct ctrl_reg, reserved
[all...]
/kernel/linux/linux-5.10/drivers/clk/hisilicon/
H A Dclk-hix5hd2.c136 u32 ctrl_reg; member
148 void __iomem *ctrl_reg; member
174 val = readl_relaxed(clk->ctrl_reg); in clk_ether_prepare()
176 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
178 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
203 val = readl_relaxed(clk->ctrl_reg); in clk_ether_unprepare()
205 writel_relaxed(val, clk->ctrl_reg); in clk_ether_unprepare()
218 val = readl_relaxed(clk->ctrl_reg); in clk_complex_enable()
221 writel_relaxed(val, clk->ctrl_reg); in clk_complex_enable()
236 val = readl_relaxed(clk->ctrl_reg); in clk_complex_disable()
[all...]
/kernel/linux/linux-6.6/drivers/clk/hisilicon/
H A Dclk-hix5hd2.c136 u32 ctrl_reg; member
148 void __iomem *ctrl_reg; member
174 val = readl_relaxed(clk->ctrl_reg); in clk_ether_prepare()
176 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
178 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
203 val = readl_relaxed(clk->ctrl_reg); in clk_ether_unprepare()
205 writel_relaxed(val, clk->ctrl_reg); in clk_ether_unprepare()
218 val = readl_relaxed(clk->ctrl_reg); in clk_complex_enable()
221 writel_relaxed(val, clk->ctrl_reg); in clk_complex_enable()
236 val = readl_relaxed(clk->ctrl_reg); in clk_complex_disable()
[all...]
/kernel/linux/linux-5.10/drivers/misc/ibmasm/
H A Dlowlevel.h53 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_enable_interrupts() local
54 writel( readl(ctrl_reg) & ~mask, ctrl_reg); in ibmasm_enable_interrupts()
59 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_disable_interrupts() local
60 writel( readl(ctrl_reg) | mask, ctrl_reg); in ibmasm_disable_interrupts()
/kernel/linux/linux-6.6/drivers/misc/ibmasm/
H A Dlowlevel.h53 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_enable_interrupts() local
54 writel( readl(ctrl_reg) & ~mask, ctrl_reg); in ibmasm_enable_interrupts()
59 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_disable_interrupts() local
60 writel( readl(ctrl_reg) | mask, ctrl_reg); in ibmasm_disable_interrupts()
/kernel/linux/linux-5.10/drivers/spi/
H A Dspi-cadence.c152 u32 ctrl_reg = CDNS_SPI_CR_DEFAULT; in cdns_spi_init_hw() local
155 ctrl_reg |= CDNS_SPI_CR_PERI_SEL; in cdns_spi_init_hw()
165 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); in cdns_spi_init_hw()
177 u32 ctrl_reg; in cdns_spi_chipselect() local
179 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR); in cdns_spi_chipselect()
183 ctrl_reg |= CDNS_SPI_CR_SSCTRL; in cdns_spi_chipselect()
186 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL; in cdns_spi_chipselect()
188 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) << in cdns_spi_chipselect()
192 ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) & in cdns_spi_chipselect()
196 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); in cdns_spi_chipselect()
208 u32 ctrl_reg, new_ctrl_reg; cdns_spi_config_clock_mode() local
251 u32 ctrl_reg, baud_rate_val; cdns_spi_config_clock_freq() local
[all...]
H A Dspi-jcore.c44 static int jcore_spi_wait(void __iomem *ctrl_reg) in jcore_spi_wait() argument
49 if (!(readl(ctrl_reg) & JCORE_SPI_STAT_BUSY)) in jcore_spi_wait()
59 void __iomem *ctrl_reg = hw->base + CTRL_REG; in jcore_spi_program() local
61 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_program()
65 writel(hw->cs_reg | hw->speed_reg, ctrl_reg); in jcore_spi_program()
101 void __iomem *ctrl_reg = hw->base + CTRL_REG; in jcore_spi_txrx() local
119 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_txrx()
123 writel(xmit, ctrl_reg); in jcore_spi_txrx()
125 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_txrx()
/kernel/linux/linux-5.10/drivers/net/wireless/st/cw1200/
H A Dbh.c178 u16 *ctrl_reg) in cw1200_bh_read_ctrl_reg()
183 ST90TDS_CONTROL_REG_ID, ctrl_reg); in cw1200_bh_read_ctrl_reg()
186 ST90TDS_CONTROL_REG_ID, ctrl_reg); in cw1200_bh_read_ctrl_reg()
196 u16 ctrl_reg; in cw1200_device_wakeup() local
213 ret = cw1200_bh_read_ctrl_reg(priv, &ctrl_reg); in cw1200_device_wakeup()
220 if (ctrl_reg & ST90TDS_CONT_RDY_BIT) { in cw1200_device_wakeup()
238 uint16_t *ctrl_reg, in cw1200_bh_rx_helper()
252 read_len = (*ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK) * 2; in cw1200_bh_rx_helper()
259 read_len, *ctrl_reg); in cw1200_bh_rx_helper()
293 *ctrl_reg in cw1200_bh_rx_helper()
177 cw1200_bh_read_ctrl_reg(struct cw1200_common *priv, u16 *ctrl_reg) cw1200_bh_read_ctrl_reg() argument
237 cw1200_bh_rx_helper(struct cw1200_common *priv, uint16_t *ctrl_reg, int *tx) cw1200_bh_rx_helper() argument
424 u16 ctrl_reg = 0; cw1200_bh() local
[all...]
/kernel/linux/linux-6.6/drivers/net/wireless/st/cw1200/
H A Dbh.c173 u16 *ctrl_reg) in cw1200_bh_read_ctrl_reg()
178 ST90TDS_CONTROL_REG_ID, ctrl_reg); in cw1200_bh_read_ctrl_reg()
181 ST90TDS_CONTROL_REG_ID, ctrl_reg); in cw1200_bh_read_ctrl_reg()
191 u16 ctrl_reg; in cw1200_device_wakeup() local
208 ret = cw1200_bh_read_ctrl_reg(priv, &ctrl_reg); in cw1200_device_wakeup()
215 if (ctrl_reg & ST90TDS_CONT_RDY_BIT) { in cw1200_device_wakeup()
233 uint16_t *ctrl_reg, in cw1200_bh_rx_helper()
247 read_len = (*ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK) * 2; in cw1200_bh_rx_helper()
254 read_len, *ctrl_reg); in cw1200_bh_rx_helper()
288 *ctrl_reg in cw1200_bh_rx_helper()
172 cw1200_bh_read_ctrl_reg(struct cw1200_common *priv, u16 *ctrl_reg) cw1200_bh_read_ctrl_reg() argument
232 cw1200_bh_rx_helper(struct cw1200_common *priv, uint16_t *ctrl_reg, int *tx) cw1200_bh_rx_helper() argument
413 u16 ctrl_reg = 0; cw1200_bh() local
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/kernel/linux/linux-5.10/drivers/staging/wfx/
H A Dbh.c139 int ctrl_reg, piggyback; in bh_work_rx() local
144 ctrl_reg = piggyback; in bh_work_rx()
146 ctrl_reg = atomic_xchg(&wdev->hif.ctrl_reg, 0); in bh_work_rx()
148 ctrl_reg = 0; in bh_work_rx()
149 if (!(ctrl_reg & CTRL_NEXT_LEN_MASK)) in bh_work_rx()
151 // ctrl_reg units are 16bits words in bh_work_rx()
152 len = (ctrl_reg & CTRL_NEXT_LEN_MASK) * 2; in bh_work_rx()
161 ctrl_reg = atomic_xchg(&wdev->hif.ctrl_reg, piggybac in bh_work_rx()
[all...]
/kernel/linux/linux-6.6/drivers/net/wireless/silabs/wfx/
H A Dbh.c137 int ctrl_reg, piggyback; in bh_work_rx() local
142 ctrl_reg = piggyback; in bh_work_rx()
144 ctrl_reg = atomic_xchg(&wdev->hif.ctrl_reg, 0); in bh_work_rx()
146 ctrl_reg = 0; in bh_work_rx()
147 if (!(ctrl_reg & CTRL_NEXT_LEN_MASK)) in bh_work_rx()
149 /* ctrl_reg units are 16bits words */ in bh_work_rx()
150 len = (ctrl_reg & CTRL_NEXT_LEN_MASK) * 2; in bh_work_rx()
159 ctrl_reg = atomic_xchg(&wdev->hif.ctrl_reg, piggybac in bh_work_rx()
[all...]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/ixgb/
H A Dixgb_hw.c49 u32 ctrl_reg; in ixgb_mac_reset() local
51 ctrl_reg = IXGB_CTRL0_RST | in ixgb_mac_reset()
62 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg); in ixgb_mac_reset()
64 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); in ixgb_mac_reset()
69 ctrl_reg = IXGB_READ_REG(hw, CTRL0); in ixgb_mac_reset()
72 ASSERT(!(ctrl_reg & IXGB_CTRL0_RST)); in ixgb_mac_reset()
76 ctrl_reg = /* Enable interrupt from XFP and SerDes */ in ixgb_mac_reset()
82 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg); in ixgb_mac_reset()
89 return ctrl_reg; in ixgb_mac_reset()
100 u32 ctrl_reg; in ixgb_adapter_stop() local
613 u32 ctrl_reg; ixgb_setup_fc() local
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