| /kernel/linux/linux-5.10/drivers/spi/ |
| H A D | spi-cavium.c | 38 bool cpha, cpol; in octeon_spi_do_transfer() local
45 cpha = mode & SPI_CPHA; in octeon_spi_do_transfer()
56 mpi_cfg.s.idlelo = cpha != cpol; in octeon_spi_do_transfer()
57 mpi_cfg.s.cslate = cpha ? 1 : 0; in octeon_spi_do_transfer()
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| H A D | spi-slave-mt27xx.c | 117 bool cpha, cpol; in mtk_spi_slave_prepare_message() local
120 cpha = spi->mode & SPI_CPHA ? 1 : 0; in mtk_spi_slave_prepare_message()
124 if (cpha) in mtk_spi_slave_prepare_message()
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| H A D | spi-geni-qcom.c | 294 u32 loopback_cfg = 0, cpol = 0, cpha = 0, demux_output_inv = 0; in setup_fifo_params() local
305 cpha = CPHA; in setup_fifo_params()
316 writel(cpha, se->base + SE_SPI_CPHA); in setup_fifo_params()
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| H A D | spi-mt65xx.c | 198 u16 cpha, cpol; in mtk_spi_prepare_message() local
204 cpha = spi->mode & SPI_CPHA ? 1 : 0; in mtk_spi_prepare_message()
208 if (cpha) in mtk_spi_prepare_message()
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| H A D | spi-stm32.c | 196 * @cpha: clock phase register and phase bit
207 const struct stm32_spi_reg cpha; member
326 .cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA },
344 .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
1018 setb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
1020 clrb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
1027 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n", in stm32_spi_prepare_msg()
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| H A D | spi-sh-msiof.c | 347 u32 cpol, u32 cpha, in sh_msiof_spi_set_pin_regs()
381 edge = cpol ^ !cpha; in sh_msiof_spi_set_pin_regs()
346 sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss, u32 cpol, u32 cpha, u32 tx_hi_z, u32 lsb_first, u32 cs_high) sh_msiof_spi_set_pin_regs() argument
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| /kernel/linux/linux-6.6/drivers/spi/ |
| H A D | spi-cavium.c | 38 bool cpha, cpol; in octeon_spi_do_transfer() local
45 cpha = mode & SPI_CPHA; in octeon_spi_do_transfer()
56 mpi_cfg.s.idlelo = cpha != cpol; in octeon_spi_do_transfer()
57 mpi_cfg.s.cslate = cpha ? 1 : 0; in octeon_spi_do_transfer()
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| H A D | spi-slave-mt27xx.c | 134 bool cpha, cpol; in mtk_spi_slave_prepare_message() local
137 cpha = spi->mode & SPI_CPHA ? 1 : 0; in mtk_spi_slave_prepare_message()
141 if (cpha) in mtk_spi_slave_prepare_message()
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| H A D | spi-stm32.c | 196 * @cpha: clock phase register and phase bit
208 const struct stm32_spi_reg cpha; member
333 .cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA },
352 .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA },
987 setb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
989 clrb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
1001 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n", in stm32_spi_prepare_msg()
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| H A D | spi-geni-qcom.c | 402 u32 loopback_cfg = 0, cpol = 0, cpha = 0, demux_output_inv = 0; in setup_fifo_params() local
413 cpha = CPHA; in setup_fifo_params()
424 writel(cpha, se->base + SE_SPI_CPHA); in setup_fifo_params()
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| H A D | spi-mt65xx.c | 353 u16 cpha, cpol; in mtk_spi_hw_init() local
358 cpha = spi->mode & SPI_CPHA ? 1 : 0; in mtk_spi_hw_init()
371 if (cpha) in mtk_spi_hw_init()
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| H A D | spi-sh-msiof.c | 350 u32 cpol, u32 cpha, in sh_msiof_spi_set_pin_regs()
384 edge = cpol ^ !cpha; in sh_msiof_spi_set_pin_regs()
349 sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss, u32 cpol, u32 cpha, u32 tx_hi_z, u32 lsb_first, u32 cs_high) sh_msiof_spi_set_pin_regs() argument
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| H A D | spi-imx.c | 635 bool cpha = (spi->mode & SPI_CPHA); in mx51_configure_cpha() local
640 /* Flip cpha logical value iff flip_cpha */ in mx51_configure_cpha()
641 cpha ^= flip_cpha; in mx51_configure_cpha()
643 if (cpha) in mx51_configure_cpha()
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