| /kernel/linux/linux-5.10/drivers/soc/xilinx/ |
| H A D | xlnx_vcu.c | 103 * @coreclk: core clock frequency
111 u32 coreclk; member
296 u32 refclk, coreclk, mcuclk, inte, deci; in xvcu_set_vcu_pll_info() local
305 coreclk = xvcu_read(xvcu->logicore_reg_ba, VCU_CORE_CLK) * MHZ; in xvcu_set_vcu_pll_info()
307 if (!mcuclk || !coreclk) { in xvcu_set_vcu_pll_info()
314 dev_dbg(xvcu->dev, "Core clock from logicoreIP is %uHz\n", coreclk); in xvcu_set_vcu_pll_info()
351 mod = pll_clk % coreclk; in xvcu_set_vcu_pll_info()
353 divisor_core = pll_clk / coreclk; in xvcu_set_vcu_pll_info()
354 } else if (coreclk - mod < LIMIT) { in xvcu_set_vcu_pll_info()
355 divisor_core = pll_clk / coreclk; in xvcu_set_vcu_pll_info()
[all...] |
| /kernel/linux/linux-6.6/drivers/pci/controller/dwc/ |
| H A D | pcie-visconti.c | 33 struct clk *coreclk; member
264 pcie->coreclk = devm_clk_get(dev, "core"); in visconti_get_resources()
265 if (IS_ERR(pcie->coreclk)) in visconti_get_resources()
266 return dev_err_probe(dev, PTR_ERR(pcie->coreclk), in visconti_get_resources()
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| /kernel/linux/linux-5.10/arch/c6x/kernel/ |
| H A D | setup.c | 91 struct clk *coreclk = clk_get_sys(NULL, "core"); in get_cpuinfo() local
99 if (!IS_ERR(coreclk)) in get_cpuinfo()
100 c6x_core_freq = clk_get_rate(coreclk); in get_cpuinfo()
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| /kernel/linux/linux-5.10/sound/soc/fsl/ |
| H A D | fsl_esai.c | 40 * @coreclk: clock source to access register
66 struct clk *coreclk; member
991 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core"); in fsl_esai_probe()
992 if (IS_ERR(esai_priv->coreclk)) { in fsl_esai_probe()
994 PTR_ERR(esai_priv->coreclk)); in fsl_esai_probe()
995 return PTR_ERR(esai_priv->coreclk); in fsl_esai_probe()
1116 ret = clk_prepare_enable(esai->coreclk); in fsl_esai_runtime_resume()
1153 clk_disable_unprepare(esai->coreclk); in fsl_esai_runtime_resume()
1170 clk_disable_unprepare(esai->coreclk); in fsl_esai_runtime_suspend()
|
| H A D | fsl_spdif.c | 98 * @coreclk: core clock for register access via DMA
119 struct clk *coreclk; member
1313 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); in fsl_spdif_probe()
1314 if (IS_ERR(spdif_priv->coreclk)) { in fsl_spdif_probe()
1316 return PTR_ERR(spdif_priv->coreclk); in fsl_spdif_probe()
1408 clk_disable_unprepare(spdif_priv->coreclk); in fsl_spdif_runtime_suspend()
1419 ret = clk_prepare_enable(spdif_priv->coreclk); in fsl_spdif_runtime_resume()
1464 clk_disable_unprepare(spdif_priv->coreclk); in fsl_spdif_runtime_resume()
|
| /kernel/linux/linux-6.6/sound/soc/fsl/ |
| H A D | fsl_esai.c | 38 * @coreclk: clock source to access register
64 struct clk *coreclk; member
984 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core"); in fsl_esai_probe()
985 if (IS_ERR(esai_priv->coreclk)) { in fsl_esai_probe()
987 PTR_ERR(esai_priv->coreclk)); in fsl_esai_probe()
988 return PTR_ERR(esai_priv->coreclk); in fsl_esai_probe()
1132 ret = clk_prepare_enable(esai->coreclk); in fsl_esai_runtime_resume()
1169 clk_disable_unprepare(esai->coreclk); in fsl_esai_runtime_resume()
1186 clk_disable_unprepare(esai->coreclk); in fsl_esai_runtime_suspend()
|
| H A D | fsl_spdif.c | 115 * @coreclk: core clock for register access via DMA
141 struct clk *coreclk; member
1598 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); in fsl_spdif_probe()
1599 if (IS_ERR(spdif_priv->coreclk)) { in fsl_spdif_probe()
1601 return PTR_ERR(spdif_priv->coreclk); in fsl_spdif_probe()
1690 clk_disable_unprepare(spdif_priv->coreclk); in fsl_spdif_runtime_suspend()
1701 ret = clk_prepare_enable(spdif_priv->coreclk); in fsl_spdif_runtime_resume()
1740 clk_disable_unprepare(spdif_priv->coreclk); in fsl_spdif_runtime_resume()
|
| /kernel/linux/linux-5.10/drivers/clk/ |
| H A D | clk-qoriq.c | 89 struct clk *sysclk, *coreclk; member
1155 clk = input_clock_by_name(name, "coreclk"); in create_coreclk()
1160 * This indicates a mix of legacy nodes with the new coreclk in create_coreclk()
1162 * don't use the wrong input clock just because coreclk isn't in create_coreclk()
1196 if (cg->coreclk && idx != PLATFORM_PLL) { in create_one_pll()
1197 if (IS_ERR(cg->coreclk)) in create_one_pll()
1200 input = "cg-coreclk"; in create_one_pll()
1406 clk = cg->coreclk; in clockgen_clk_get()
1521 clockgen.coreclk = create_coreclk("cg-coreclk"); in _clockgen_init()
[all...] |
| /kernel/linux/linux-6.6/drivers/clk/ |
| H A D | clk-qoriq.c | 91 struct clk *sysclk, *coreclk; member
1181 clk = input_clock_by_name(name, "coreclk"); in create_coreclk()
1186 * This indicates a mix of legacy nodes with the new coreclk in create_coreclk()
1188 * don't use the wrong input clock just because coreclk isn't in create_coreclk()
1222 if (cg->coreclk && idx != PLATFORM_PLL) { in create_one_pll()
1223 if (IS_ERR(cg->coreclk)) in create_one_pll()
1226 input = "cg-coreclk"; in create_one_pll()
1432 clk = cg->coreclk; in clockgen_clk_get()
1547 clockgen.coreclk = create_coreclk("cg-coreclk"); in _clockgen_init()
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| H A D | intel_dpll.c | 1666 u32 coreclk, reg_val; in vlv_prepare_pll() local
1738 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); in vlv_prepare_pll()
1739 coreclk = (coreclk & 0x0000ff00) | 0x01c00000; in vlv_prepare_pll()
1741 coreclk |= 0x01000000; in vlv_prepare_pll()
1742 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); in vlv_prepare_pll()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| H A D | intel_display.c | 8434 u32 coreclk, reg_val; in vlv_prepare_pll() local
8514 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); in vlv_prepare_pll()
8515 coreclk = (coreclk & 0x0000ff00) | 0x01c00000; in vlv_prepare_pll()
8517 coreclk |= 0x01000000; in vlv_prepare_pll()
8518 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); in vlv_prepare_pll()
|