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Searched refs:clk_name (Results 1 - 25 of 278) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dp/
H A Ddp_parser.c104 const char *clk_name) in dp_parser_check_prefix()
106 return !strncmp(clk_prefix, clk_name, strlen(clk_prefix)); in dp_parser_check_prefix()
113 const char *clk_name; in dp_parser_init_clk_data() local
127 "clock-names", i, &clk_name); in dp_parser_init_clk_data()
131 if (dp_parser_check_prefix("core", clk_name)) in dp_parser_init_clk_data()
134 if (dp_parser_check_prefix("ctrl", clk_name)) in dp_parser_init_clk_data()
137 if (dp_parser_check_prefix("stream", clk_name)) in dp_parser_init_clk_data()
193 const char *clk_name; in dp_parser_clock() local
213 i, &clk_name); in dp_parser_clock()
218 if (dp_parser_check_prefix("core", clk_name) in dp_parser_clock()
103 dp_parser_check_prefix(const char *clk_prefix, const char *clk_name) dp_parser_check_prefix() argument
[all...]
/kernel/linux/linux-5.10/drivers/clk/zynqmp/
H A Dpll.c52 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_get_mode() local
59 __func__, clk_name, ret); in zynqmp_pll_get_mode()
73 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_set_mode() local
85 __func__, clk_name, ret); in zynqmp_pll_set_mode()
135 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_recalc_rate() local
144 __func__, clk_name, ret); in zynqmp_pll_recalc_rate()
172 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_set_rate() local
190 clk_name); in zynqmp_pll_set_rate()
193 __func__, clk_name, ret); in zynqmp_pll_set_rate()
204 __func__, clk_name, re in zynqmp_pll_set_rate()
218 const char *clk_name = clk_hw_get_name(hw); zynqmp_pll_is_enabled() local
242 const char *clk_name = clk_hw_get_name(hw); zynqmp_pll_enable() local
270 const char *clk_name = clk_hw_get_name(hw); zynqmp_pll_disable() local
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H A Dclk-gate-zynqmp.c37 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_enable() local
45 __func__, clk_name, ret); in zynqmp_clk_gate_enable()
57 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_disable() local
65 __func__, clk_name, ret); in zynqmp_clk_gate_disable()
77 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_is_enabled() local
84 __func__, clk_name, ret); in zynqmp_clk_gate_is_enabled()
H A Dclkc.c61 * @clk_name: Clock name
71 char clk_name[MAX_NAME_LEN]; member
156 * @clk_name: Name of clock
160 static int zynqmp_get_clock_name(u32 clk_id, char *clk_name) in zynqmp_get_clock_name() argument
166 strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN); in zynqmp_get_clock_name()
552 * @clk_name: Clock Name
558 static struct clk_hw *zynqmp_register_clk_topology(int clk_id, char *clk_name, in zynqmp_register_clk_topology() argument
578 clk_out[j] = kasprintf(GFP_KERNEL, "%s%s", clk_name, in zynqmp_register_clk_topology()
581 clk_out[j] = kasprintf(GFP_KERNEL, "%s", clk_name); in zynqmp_register_clk_topology()
618 char clk_name[MAX_NAME_LEN]; zynqmp_register_clocks() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/zynqmp/
H A Dpll.c53 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_get_mode() local
60 __func__, clk_name, ret); in zynqmp_pll_get_mode()
76 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_set_mode() local
88 __func__, clk_name, ret); in zynqmp_pll_set_mode()
138 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_recalc_rate() local
148 __func__, clk_name, ret); in zynqmp_pll_recalc_rate()
182 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_set_rate() local
200 clk_name); in zynqmp_pll_set_rate()
203 __func__, clk_name, ret); in zynqmp_pll_set_rate()
214 __func__, clk_name, re in zynqmp_pll_set_rate()
228 const char *clk_name = clk_hw_get_name(hw); zynqmp_pll_is_enabled() local
252 const char *clk_name = clk_hw_get_name(hw); zynqmp_pll_enable() local
280 const char *clk_name = clk_hw_get_name(hw); zynqmp_pll_disable() local
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H A Dclk-gate-zynqmp.c37 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_enable() local
45 __func__, clk_name, clk_id, ret); in zynqmp_clk_gate_enable()
57 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_disable() local
65 __func__, clk_name, clk_id, ret); in zynqmp_clk_gate_disable()
77 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_is_enabled() local
84 __func__, clk_name, ret); in zynqmp_clk_gate_is_enabled()
/kernel/linux/linux-5.10/drivers/mailbox/
H A Dqcom-apcs-ipc-mailbox.c29 char *clk_name; member
33 .offset = 8, .clk_name = "qcom,apss-ipq6018-clk"
37 .offset = 8, .clk_name = NULL
41 .offset = 8, .clk_name = "qcom-apcs-msm8916-clk"
45 .offset = 8, .clk_name = NULL
49 .offset = 16, .clk_name = NULL
53 .offset = 8, .clk_name = NULL
57 .offset = 8, .clk_name = NULL
61 .offset = 12, .clk_name = NULL
128 if (apcs_data->clk_name) { in qcom_apcs_ipc_probe()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_io_util.c32 clk_arry[i].clk = clk_get(dev, clk_arry[i].clk_name); in msm_dss_get_clk()
37 clk_arry[i].clk_name, rc); in msm_dss_get_clk()
63 clk_arry[i].clk_name, in msm_dss_clk_set_rate()
71 clk_arry[i].clk_name, rc); in msm_dss_clk_set_rate()
78 clk_arry[i].clk_name); in msm_dss_clk_set_rate()
95 clk_arry[i].clk_name); in msm_dss_enable_clk()
101 clk_arry[i].clk_name, rc); in msm_dss_enable_clk()
113 clk_arry[i].clk_name); in msm_dss_enable_clk()
154 strlcpy(mp->clk_config[i].clk_name, clock_name, in msm_dss_parse_clock()
155 sizeof(mp->clk_config[i].clk_name)); in msm_dss_parse_clock()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dp/
H A Ddp_parser.c145 const char *clk_name) in dp_parser_check_prefix()
147 return !strncmp(clk_prefix, clk_name, strlen(clk_prefix)); in dp_parser_check_prefix()
154 const char *clk_name; in dp_parser_init_clk_data() local
168 "clock-names", i, &clk_name); in dp_parser_init_clk_data()
172 if (dp_parser_check_prefix("core", clk_name)) in dp_parser_init_clk_data()
175 if (dp_parser_check_prefix("ctrl", clk_name)) in dp_parser_init_clk_data()
178 if (dp_parser_check_prefix("stream", clk_name)) in dp_parser_init_clk_data()
234 const char *clk_name; in dp_parser_clock() local
254 i, &clk_name); in dp_parser_clock()
259 if (dp_parser_check_prefix("core", clk_name) in dp_parser_clock()
144 dp_parser_check_prefix(const char *clk_prefix, const char *clk_name) dp_parser_check_prefix() argument
[all...]
/kernel/linux/linux-5.10/drivers/clk/sunxi/
H A Dclk-a10-pll2.c41 const char *clk_name = node->name, *parent; in sun4i_pll2_setup() local
121 SUN4I_A10_PLL2_1X, &clk_name); in sun4i_pll2_setup()
122 clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
136 SUN4I_A10_PLL2_2X, &clk_name); in sun4i_pll2_setup()
137 clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
145 SUN4I_A10_PLL2_4X, &clk_name); in sun4i_pll2_setup()
146 clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
154 SUN4I_A10_PLL2_8X, &clk_name); in sun4i_pll2_setup()
155 clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
H A Dclk-sun4i-pll3.c23 const char *clk_name = node->name, *parent; in sun4i_a10_pll3_setup() local
31 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_a10_pll3_setup()
36 pr_err("%s: Could not map the clock registers\n", clk_name); in sun4i_a10_pll3_setup()
57 clk = clk_register_composite(NULL, clk_name, in sun4i_a10_pll3_setup()
64 pr_err("%s: Couldn't register the clock\n", clk_name); in sun4i_a10_pll3_setup()
71 clk_name); in sun4i_a10_pll3_setup()
H A Dclk-sun4i-display.c105 const char *clk_name = node->name; in sun4i_a10_display_init() local
115 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_a10_display_init()
119 pr_err("%s: Could not map the clock registers\n", clk_name); in sun4i_a10_display_init()
125 pr_err("%s: Could not retrieve the parents\n", clk_name); in sun4i_a10_display_init()
157 clk = clk_register_composite(NULL, clk_name, in sun4i_a10_display_init()
165 pr_err("%s: Couldn't register the clock\n", clk_name); in sun4i_a10_display_init()
171 pr_err("%s: Couldn't register DT provider\n", clk_name); in sun4i_a10_display_init()
198 clk_name); in sun4i_a10_display_init()
/kernel/linux/linux-6.6/drivers/clk/sunxi/
H A Dclk-a10-pll2.c41 const char *clk_name = node->name, *parent; in sun4i_pll2_setup() local
121 SUN4I_A10_PLL2_1X, &clk_name); in sun4i_pll2_setup()
122 clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
136 SUN4I_A10_PLL2_2X, &clk_name); in sun4i_pll2_setup()
137 clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
145 SUN4I_A10_PLL2_4X, &clk_name); in sun4i_pll2_setup()
146 clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
154 SUN4I_A10_PLL2_8X, &clk_name); in sun4i_pll2_setup()
155 clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
H A Dclk-sun4i-pll3.c23 const char *clk_name = node->name, *parent; in sun4i_a10_pll3_setup() local
31 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_a10_pll3_setup()
36 pr_err("%s: Could not map the clock registers\n", clk_name); in sun4i_a10_pll3_setup()
57 clk = clk_register_composite(NULL, clk_name, in sun4i_a10_pll3_setup()
64 pr_err("%s: Couldn't register the clock\n", clk_name); in sun4i_a10_pll3_setup()
71 clk_name); in sun4i_a10_pll3_setup()
H A Dclk-sun4i-display.c105 const char *clk_name = node->name; in sun4i_a10_display_init() local
115 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_a10_display_init()
119 pr_err("%s: Could not map the clock registers\n", clk_name); in sun4i_a10_display_init()
125 pr_err("%s: Could not retrieve the parents\n", clk_name); in sun4i_a10_display_init()
157 clk = clk_register_composite(NULL, clk_name, in sun4i_a10_display_init()
165 pr_err("%s: Couldn't register the clock\n", clk_name); in sun4i_a10_display_init()
171 pr_err("%s: Couldn't register DT provider\n", clk_name); in sun4i_a10_display_init()
198 clk_name); in sun4i_a10_display_init()
/kernel/linux/linux-6.6/drivers/mailbox/
H A Dqcom-apcs-ipc-mailbox.c29 char *clk_name; member
33 .offset = 8, .clk_name = "qcom,apss-ipq6018-clk"
37 .offset = 8, .clk_name = "qcom-apcs-msm8916-clk"
41 .offset = 8, .clk_name = NULL
45 .offset = 16, .clk_name = "qcom-apcs-msm8996-clk"
49 .offset = 12, .clk_name = NULL
53 .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk"
118 if (apcs_data->clk_name) { in qcom_apcs_ipc_probe()
120 apcs_data->clk_name, in qcom_apcs_ipc_probe()
/kernel/linux/linux-5.10/drivers/clk/pxa/
H A Dclk-pxa.h19 #define MUX_RO_RATE_RO_OPS(name, clk_name) \
31 return clk_register_composite(NULL, clk_name, \
39 #define RATE_RO_OPS(name, clk_name) \
46 return clk_register_composite(NULL, clk_name, \
54 #define RATE_OPS(name, clk_name) \
63 return clk_register_composite(NULL, clk_name, \
71 #define MUX_OPS(name, clk_name, flags) \
80 return clk_register_composite(NULL, clk_name, \
/kernel/linux/linux-6.6/drivers/clk/pxa/
H A Dclk-pxa.h19 #define MUX_RO_RATE_RO_OPS(name, clk_name) \
31 return clk_register_composite(NULL, clk_name, \
39 #define RATE_RO_OPS(name, clk_name) \
46 return clk_register_composite(NULL, clk_name, \
54 #define RATE_OPS(name, clk_name) \
63 return clk_register_composite(NULL, clk_name, \
71 #define MUX_OPS(name, clk_name, flags) \
80 return clk_register_composite(NULL, clk_name, \
/kernel/linux/linux-5.10/drivers/clk/h8300/
H A Dclk-div.c20 const char *clk_name = node->name; in h8300_div_clk_setup() local
28 pr_err("%s: no parent found\n", clk_name); in h8300_div_clk_setup()
34 pr_err("%s: failed to map divide register\n", clk_name); in h8300_div_clk_setup()
43 hw = clk_hw_register_divider(NULL, clk_name, parent_name, in h8300_div_clk_setup()
51 __func__, clk_name, PTR_ERR(hw)); in h8300_div_clk_setup()
H A Dclk-h8s2678.c89 const char *clk_name = node->name; in h8s2678_pll_clk_setup() local
97 pr_err("%s: no parent found\n", clk_name); in h8s2678_pll_clk_setup()
108 pr_err("%s: failed to map divide register\n", clk_name); in h8s2678_pll_clk_setup()
114 pr_err("%s: failed to map multiply register\n", clk_name); in h8s2678_pll_clk_setup()
119 init.name = clk_name; in h8s2678_pll_clk_setup()
129 __func__, clk_name, ret); in h8s2678_pll_clk_setup()
/kernel/linux/linux-5.10/arch/m68k/include/asm/
H A Dmcfclk.h35 #define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \
37 .name = clk_name, \
46 #define DEFINE_CLK(clk_ref, clk_name, clk_rate) \
48 .name = clk_name, \
/kernel/linux/linux-5.10/drivers/staging/clocking-wizard/
H A Dclk-xlnx-clock-wizard.c136 const char *clk_name; in clk_wzrd_probe() local
195 clk_name = kasprintf(GFP_KERNEL, "%s_mul", dev_name(&pdev->dev)); in clk_wzrd_probe()
196 if (!clk_name) { in clk_wzrd_probe()
201 (&pdev->dev, clk_name, in clk_wzrd_probe()
204 kfree(clk_name); in clk_wzrd_probe()
214 clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev)); in clk_wzrd_probe()
215 if (!clk_name) { in clk_wzrd_probe()
221 (&pdev->dev, clk_name, in clk_wzrd_probe()
245 (&pdev->dev, clkout_name, clk_name, 0, 1, reg); in clk_wzrd_probe()
258 kfree(clk_name); in clk_wzrd_probe()
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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_10nm.c577 char clk_name[32]; in pll_10nm_register() local
583 .name = clk_name, in pll_10nm_register()
594 snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_10nm->phy->id); in pll_10nm_register()
601 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_out_div_clk", pll_10nm->phy->id); in pll_10nm_register()
603 pll_out_div = devm_clk_hw_register_divider_parent_hw(dev, clk_name, in pll_10nm_register()
613 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_bit_clk", pll_10nm->phy->id); in pll_10nm_register()
616 pll_bit = devm_clk_hw_register_divider_parent_hw(dev, clk_name, in pll_10nm_register()
[all...]
/kernel/linux/linux-5.10/drivers/clk/mvebu/
H A Dclk-cpu.c36 const char *clk_name; member
198 char *clk_name = kzalloc(5, GFP_KERNEL); in of_cpu_clk_setup() local
201 if (WARN_ON(!clk_name)) in of_cpu_clk_setup()
208 sprintf(clk_name, "cpu%d", cpu); in of_cpu_clk_setup()
211 cpuclk[cpu].clk_name = clk_name; in of_cpu_clk_setup()
218 init.name = cpuclk[cpu].clk_name; in of_cpu_clk_setup()
237 kfree(cpuclk[ncpus].clk_name); in of_cpu_clk_setup()
/kernel/linux/linux-6.6/drivers/clk/mvebu/
H A Dclk-cpu.c36 const char *clk_name; member
195 char *clk_name = kzalloc(5, GFP_KERNEL); in of_cpu_clk_setup() local
197 if (WARN_ON(!clk_name)) in of_cpu_clk_setup()
200 sprintf(clk_name, "cpu%d", cpu); in of_cpu_clk_setup()
203 cpuclk[cpu].clk_name = clk_name; in of_cpu_clk_setup()
210 init.name = cpuclk[cpu].clk_name; in of_cpu_clk_setup()
229 kfree(cpuclk[ncpus].clk_name); in of_cpu_clk_setup()

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