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Help
Searched
refs:WR_CONFIRM
(Results
1 - 22
of
22
) sorted by relevance
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H
A
D
nvd.h
98
#define
WR_CONFIRM
(1 << 20)
macro
H
A
D
soc15d.h
119
#define
WR_CONFIRM
(1 << 20)
macro
H
A
D
cikd.h
269
#define
WR_CONFIRM
(1 << 20)
macro
H
A
D
vid.h
151
#define
WR_CONFIRM
(1 << 20)
macro
H
A
D
gfx_v9_0.c
1011
(wc ?
WR_CONFIRM
: 0));
in gfx_v9_0_write_data_to_reg()
1100
ib.ptr[1] = WRITE_DATA_DST_SEL(5) |
WR_CONFIRM
;
in gfx_v9_0_ring_test_ib()
5440
WRITE_DATA_DST_SEL(5) |
WR_CONFIRM
));
in gfx_v9_0_ring_emit_fence_kiq()
5449
WRITE_DATA_DST_SEL(0) |
WR_CONFIRM
));
in gfx_v9_0_ring_emit_fence_kiq()
5474
WR_CONFIRM
) |
in gfx_v9_0_ring_emit_ce_meta()
5496
WR_CONFIRM
) |
in gfx_v9_0_ring_emit_de_meta()
5593
cmd = WRITE_DATA_ENGINE_SEL(1) |
WR_CONFIRM
;
in gfx_v9_0_ring_emit_wreg()
5599
cmd =
WR_CONFIRM
;
in gfx_v9_0_ring_emit_wreg()
H
A
D
gfx_v8_0.c
897
ib.ptr[1] = WRITE_DATA_DST_SEL(5) |
WR_CONFIRM
;
in gfx_v8_0_ring_test_ib()
6303
WRITE_DATA_DST_SEL(5) |
WR_CONFIRM
));
in gfx_v8_0_ring_emit_fence_kiq()
6312
WRITE_DATA_DST_SEL(0) |
WR_CONFIRM
));
in gfx_v8_0_ring_emit_fence_kiq()
6409
cmd = WRITE_DATA_ENGINE_SEL(1) |
WR_CONFIRM
;
in gfx_v8_0_ring_emit_wreg()
6415
cmd =
WR_CONFIRM
;
in gfx_v8_0_ring_emit_wreg()
7156
WR_CONFIRM
) |
in gfx_v8_0_ring_emit_ce_meta()
7189
WR_CONFIRM
) |
in gfx_v8_0_ring_emit_de_meta()
H
A
D
gfx_v10_0.c
3420
WRITE_DATA_DST_SEL(0) | (wc ?
WR_CONFIRM
: 0));
in gfx_v10_0_write_data_to_reg()
3518
ib.ptr[1] = WRITE_DATA_DST_SEL(5) |
WR_CONFIRM
;
in gfx_v10_0_ring_test_ib()
7928
WRITE_DATA_DST_SEL(5) |
WR_CONFIRM
));
in gfx_v10_0_ring_emit_fence_kiq()
7937
WRITE_DATA_DST_SEL(0) |
WR_CONFIRM
));
in gfx_v10_0_ring_emit_fence_kiq()
8071
WR_CONFIRM
) |
in gfx_v10_0_ring_emit_ce_meta()
8105
WR_CONFIRM
) |
in gfx_v10_0_ring_emit_de_meta()
8155
cmd = WRITE_DATA_ENGINE_SEL(1) |
WR_CONFIRM
;
in gfx_v10_0_ring_emit_wreg()
8161
cmd =
WR_CONFIRM
;
in gfx_v10_0_ring_emit_wreg()
H
A
D
sid.h
1709
#define
WR_CONFIRM
(1 << 20)
macro
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H
A
D
nvd.h
98
#define
WR_CONFIRM
(1 << 20)
macro
H
A
D
soc15d.h
119
#define
WR_CONFIRM
(1 << 20)
macro
H
A
D
cikd.h
269
#define
WR_CONFIRM
(1 << 20)
macro
H
A
D
vid.h
151
#define
WR_CONFIRM
(1 << 20)
macro
H
A
D
gfx_v9_4_3.c
219
(wc ?
WR_CONFIRM
: 0));
in gfx_v9_4_3_write_data_to_reg()
305
ib.ptr[1] = WRITE_DATA_DST_SEL(5) |
WR_CONFIRM
;
in gfx_v9_4_3_ring_test_ib()
2634
WRITE_DATA_DST_SEL(5) |
WR_CONFIRM
));
in gfx_v9_4_3_ring_emit_fence_kiq()
2643
WRITE_DATA_DST_SEL(0) |
WR_CONFIRM
));
in gfx_v9_4_3_ring_emit_fence_kiq()
2674
cmd = WRITE_DATA_ENGINE_SEL(1) |
WR_CONFIRM
;
in gfx_v9_4_3_ring_emit_wreg()
2680
cmd =
WR_CONFIRM
;
in gfx_v9_4_3_ring_emit_wreg()
H
A
D
gfx_v9_0.c
966
(wc ?
WR_CONFIRM
: 0));
in gfx_v9_0_write_data_to_reg()
1048
ib.ptr[1] = WRITE_DATA_DST_SEL(5) |
WR_CONFIRM
;
in gfx_v9_0_ring_test_ib()
5393
WRITE_DATA_DST_SEL(5) |
WR_CONFIRM
));
in gfx_v9_0_ring_emit_fence_kiq()
5402
WRITE_DATA_DST_SEL(0) |
WR_CONFIRM
));
in gfx_v9_0_ring_emit_fence_kiq()
5442
WR_CONFIRM
) |
in gfx_v9_0_ring_emit_ce_meta()
5555
WR_CONFIRM
) |
in gfx_v9_0_ring_emit_de_meta()
5660
cmd = WRITE_DATA_ENGINE_SEL(1) |
WR_CONFIRM
;
in gfx_v9_0_ring_emit_wreg()
5666
cmd =
WR_CONFIRM
;
in gfx_v9_0_ring_emit_wreg()
H
A
D
gfx_v8_0.c
892
ib.ptr[1] = WRITE_DATA_DST_SEL(5) |
WR_CONFIRM
;
in gfx_v8_0_ring_test_ib()
6275
WRITE_DATA_DST_SEL(5) |
WR_CONFIRM
));
in gfx_v8_0_ring_emit_fence_kiq()
6284
WRITE_DATA_DST_SEL(0) |
WR_CONFIRM
));
in gfx_v8_0_ring_emit_fence_kiq()
6381
cmd = WRITE_DATA_ENGINE_SEL(1) |
WR_CONFIRM
;
in gfx_v8_0_ring_emit_wreg()
6387
cmd =
WR_CONFIRM
;
in gfx_v8_0_ring_emit_wreg()
7192
WR_CONFIRM
) |
in gfx_v8_0_ring_emit_ce_meta()
7225
WR_CONFIRM
) |
in gfx_v8_0_ring_emit_de_meta()
H
A
D
gfx_v11_0.c
293
WRITE_DATA_DST_SEL(0) | (wc ?
WR_CONFIRM
: 0));
in gfx_v11_0_write_data_to_reg()
409
ib.ptr[1] = WRITE_DATA_DST_SEL(5) |
WR_CONFIRM
;
in gfx_v11_0_ring_test_ib()
5452
WRITE_DATA_DST_SEL(5) |
WR_CONFIRM
));
in gfx_v11_0_ring_emit_fence_kiq()
5461
WRITE_DATA_DST_SEL(0) |
WR_CONFIRM
));
in gfx_v11_0_ring_emit_fence_kiq()
5623
WR_CONFIRM
) |
in gfx_v11_0_ring_emit_de_meta()
5669
cmd = WRITE_DATA_ENGINE_SEL(1) |
WR_CONFIRM
;
in gfx_v11_0_ring_emit_wreg()
5675
cmd =
WR_CONFIRM
;
in gfx_v11_0_ring_emit_wreg()
H
A
D
gfx_v10_0.c
3738
WRITE_DATA_DST_SEL(0) | (wc ?
WR_CONFIRM
: 0));
in gfx_v10_0_write_data_to_reg()
3846
ib.ptr[1] = WRITE_DATA_DST_SEL(5) |
WR_CONFIRM
;
in gfx_v10_0_ring_test_ib()
8453
WRITE_DATA_DST_SEL(5) |
WR_CONFIRM
));
in gfx_v10_0_ring_emit_fence_kiq()
8462
WRITE_DATA_DST_SEL(0) |
WR_CONFIRM
));
in gfx_v10_0_ring_emit_fence_kiq()
8611
WR_CONFIRM
) |
in gfx_v10_0_ring_emit_ce_meta()
8662
WR_CONFIRM
) |
in gfx_v10_0_ring_emit_de_meta()
8708
cmd = WRITE_DATA_ENGINE_SEL(1) |
WR_CONFIRM
;
in gfx_v10_0_ring_emit_wreg()
8714
cmd =
WR_CONFIRM
;
in gfx_v10_0_ring_emit_wreg()
H
A
D
sid.h
1709
#define
WR_CONFIRM
(1 << 20)
macro
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H
A
D
cikd.h
1737
#define
WR_CONFIRM
(1 << 20)
macro
H
A
D
sid.h
1646
#define
WR_CONFIRM
(1 << 20)
macro
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H
A
D
cikd.h
1737
#define
WR_CONFIRM
(1 << 20)
macro
H
A
D
sid.h
1646
#define
WR_CONFIRM
(1 << 20)
macro
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