| /kernel/linux/linux-5.10/drivers/gpu/drm/vc4/ |
| H A D | vc4_v3d.c | 19 VC4_REG32(V3D_IDENT0),
20 VC4_REG32(V3D_IDENT1),
21 VC4_REG32(V3D_IDENT2),
22 VC4_REG32(V3D_SCRATCH),
23 VC4_REG32(V3D_L2CACTL),
24 VC4_REG32(V3D_SLCACTL),
25 VC4_REG32(V3D_INTCTL),
26 VC4_REG32(V3D_INTENA),
27 VC4_REG32(V3D_INTDIS),
28 VC4_REG32(V3D_CT0C
[all...] |
| H A D | vc4_hvs.c | 34 VC4_REG32(SCALER_DISPCTRL),
35 VC4_REG32(SCALER_DISPSTAT),
36 VC4_REG32(SCALER_DISPID),
37 VC4_REG32(SCALER_DISPECTRL),
38 VC4_REG32(SCALER_DISPPROF),
39 VC4_REG32(SCALER_DISPDITHER),
40 VC4_REG32(SCALER_DISPEOLN),
41 VC4_REG32(SCALER_DISPLIST0),
42 VC4_REG32(SCALER_DISPLIST1),
43 VC4_REG32(SCALER_DISPLIST
[all...] |
| H A D | vc4_vec.c | 219 VC4_REG32(VEC_WSE_CONTROL),
220 VC4_REG32(VEC_WSE_WSS_DATA),
221 VC4_REG32(VEC_WSE_VPS_DATA1),
222 VC4_REG32(VEC_WSE_VPS_CONTROL),
223 VC4_REG32(VEC_REVID),
224 VC4_REG32(VEC_CONFIG0),
225 VC4_REG32(VEC_SCHPH),
226 VC4_REG32(VEC_CLMP0_START),
227 VC4_REG32(VEC_CLMP0_END),
228 VC4_REG32(VEC_FREQ3_
[all...] |
| H A D | vc4_dsi.c | 660 VC4_REG32(DSI0_CTRL),
661 VC4_REG32(DSI0_STAT),
662 VC4_REG32(DSI0_HSTX_TO_CNT),
663 VC4_REG32(DSI0_LPRX_TO_CNT),
664 VC4_REG32(DSI0_TA_TO_CNT),
665 VC4_REG32(DSI0_PR_TO_CNT),
666 VC4_REG32(DSI0_DISP0_CTRL),
667 VC4_REG32(DSI0_DISP1_CTRL),
668 VC4_REG32(DSI0_INT_STAT),
669 VC4_REG32(DSI0_INT_E
[all...] |
| H A D | vc4_crtc.c | 53 VC4_REG32(PV_CONTROL),
54 VC4_REG32(PV_V_CONTROL),
55 VC4_REG32(PV_VSYNCD_EVEN),
56 VC4_REG32(PV_HORZA),
57 VC4_REG32(PV_HORZB),
58 VC4_REG32(PV_VERTA),
59 VC4_REG32(PV_VERTB),
60 VC4_REG32(PV_VERTA_EVEN),
61 VC4_REG32(PV_VERTB_EVEN),
62 VC4_REG32(PV_INTE
[all...] |
| H A D | vc4_txp.c | 170 VC4_REG32(TXP_DST_PTR),
171 VC4_REG32(TXP_DST_PITCH),
172 VC4_REG32(TXP_DIM),
173 VC4_REG32(TXP_DST_CTRL),
174 VC4_REG32(TXP_PROGRESS),
|
| H A D | vc4_dpi.c | 114 VC4_REG32(DPI_C),
115 VC4_REG32(DPI_ID),
|
| H A D | vc4_drv.h | 552 #define VC4_REG32(reg) { .name = #reg, .offset = reg } macro
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/vc4/ |
| H A D | vc4_v3d.c | 17 VC4_REG32(V3D_IDENT0),
18 VC4_REG32(V3D_IDENT1),
19 VC4_REG32(V3D_IDENT2),
20 VC4_REG32(V3D_SCRATCH),
21 VC4_REG32(V3D_L2CACTL),
22 VC4_REG32(V3D_SLCACTL),
23 VC4_REG32(V3D_INTCTL),
24 VC4_REG32(V3D_INTENA),
25 VC4_REG32(V3D_INTDIS),
26 VC4_REG32(V3D_CT0C
[all...] |
| H A D | vc4_vec.c | 248 VC4_REG32(VEC_WSE_CONTROL),
249 VC4_REG32(VEC_WSE_WSS_DATA),
250 VC4_REG32(VEC_WSE_VPS_DATA1),
251 VC4_REG32(VEC_WSE_VPS_CONTROL),
252 VC4_REG32(VEC_REVID),
253 VC4_REG32(VEC_CONFIG0),
254 VC4_REG32(VEC_SCHPH),
255 VC4_REG32(VEC_CLMP0_START),
256 VC4_REG32(VEC_CLMP0_END),
257 VC4_REG32(VEC_FREQ3_
[all...] |
| H A D | vc4_hvs.c | 37 VC4_REG32(SCALER_DISPCTRL),
38 VC4_REG32(SCALER_DISPSTAT),
39 VC4_REG32(SCALER_DISPID),
40 VC4_REG32(SCALER_DISPECTRL),
41 VC4_REG32(SCALER_DISPPROF),
42 VC4_REG32(SCALER_DISPDITHER),
43 VC4_REG32(SCALER_DISPEOLN),
44 VC4_REG32(SCALER_DISPLIST0),
45 VC4_REG32(SCALER_DISPLIST1),
46 VC4_REG32(SCALER_DISPLIST
[all...] |
| H A D | vc4_dsi.c | 665 VC4_REG32(DSI0_CTRL),
666 VC4_REG32(DSI0_STAT),
667 VC4_REG32(DSI0_HSTX_TO_CNT),
668 VC4_REG32(DSI0_LPRX_TO_CNT),
669 VC4_REG32(DSI0_TA_TO_CNT),
670 VC4_REG32(DSI0_PR_TO_CNT),
671 VC4_REG32(DSI0_DISP0_CTRL),
672 VC4_REG32(DSI0_DISP1_CTRL),
673 VC4_REG32(DSI0_INT_STAT),
674 VC4_REG32(DSI0_INT_E
[all...] |
| H A D | vc4_crtc.c | 67 VC4_REG32(PV_CONTROL),
68 VC4_REG32(PV_V_CONTROL),
69 VC4_REG32(PV_VSYNCD_EVEN),
70 VC4_REG32(PV_HORZA),
71 VC4_REG32(PV_HORZB),
72 VC4_REG32(PV_VERTA),
73 VC4_REG32(PV_VERTB),
74 VC4_REG32(PV_VERTA_EVEN),
75 VC4_REG32(PV_VERTB_EVEN),
76 VC4_REG32(PV_INTE
[all...] |
| H A D | vc4_txp.c | 178 VC4_REG32(TXP_DST_PTR),
179 VC4_REG32(TXP_DST_PITCH),
180 VC4_REG32(TXP_DIM),
181 VC4_REG32(TXP_DST_CTRL),
182 VC4_REG32(TXP_PROGRESS),
|
| H A D | vc4_dpi.c | 116 VC4_REG32(DPI_C),
117 VC4_REG32(DPI_ID),
|
| H A D | vc4_drv.h | 642 #define VC4_REG32(reg) { .name = #reg, .offset = reg } macro
|