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Searched refs:SOR_CLK_CNTRL (Results 1 - 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/tegra/
H A Dsor.c535 * the SOR_CLK_CNTRL register. This is primarily for compatibility with the
546 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
559 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
571 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_get_parent()
883 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
886 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
1551 DEBUGFS_REG32(SOR_CLK_CNTRL),
2339 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2352 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2396 * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL registe in tegra_sor_hdmi_enable()
[all...]
H A Dsor.h62 #define SOR_CLK_CNTRL 0x13 macro
/kernel/linux/linux-6.6/drivers/gpu/drm/tegra/
H A Dsor.c535 * the SOR_CLK_CNTRL register. This is primarily for compatibility with the
546 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
559 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
571 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_get_parent()
884 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
887 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
1552 DEBUGFS_REG32(SOR_CLK_CNTRL),
2335 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2348 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2392 * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL registe in tegra_sor_hdmi_enable()
[all...]
H A Dsor.h62 #define SOR_CLK_CNTRL 0x13 macro

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