| /kernel/linux/linux-5.10/drivers/dma/ |
| H A D | txx9dmac.h | 72 u64 SAR; /* Source Address Register */ member
82 u32 SAR; member
206 u64 SAR; member
212 u32 SAR; member
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| H A D | txx9dmac.c | 287 " CHAR: %#llx SAR: %#llx DAR: %#llx CNTR: %#x" in txx9dmac_dump_regs()
290 channel64_readq(dc, SAR), in txx9dmac_dump_regs()
299 " CHAR: %#x SAR: %#x DAR: %#x CNTR: %#x" in txx9dmac_dump_regs()
302 channel32_readl(dc, SAR), in txx9dmac_dump_regs()
316 channel_writeq(dc, SAR, 0); in txx9dmac_reset_chan()
320 channel_writel(dc, SAR, 0); in txx9dmac_reset_chan()
474 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR); in txx9dmac_dump_desc()
479 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR, in txx9dmac_dump_desc()
487 d->CHAR, d->SAR, d->DAR, d->CNTR); in txx9dmac_dump_desc()
492 d->CHAR, d->SAR, in txx9dmac_dump_desc()
[all...] |
| H A D | idma64.c | 94 channel_writeq(idma64c, SAR, 0); in idma64_chan_start()
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| H A D | pl330.c | 339 SAR = 0, enumerator
732 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); in _emit_MOV()
1399 /* DMAMOV SAR, x->src_addr */ in _setup_xfer()
1400 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr); in _setup_xfer()
2401 /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */ in pl330_get_current_xferred_count()
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| /kernel/linux/linux-6.6/drivers/dma/ |
| H A D | txx9dmac.h | 72 u64 SAR; /* Source Address Register */ member
82 u32 SAR; member
206 u64 SAR; member
212 u32 SAR; member
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| H A D | txx9dmac.c | 287 " CHAR: %#llx SAR: %#llx DAR: %#llx CNTR: %#x" in txx9dmac_dump_regs()
290 channel64_readq(dc, SAR), in txx9dmac_dump_regs()
299 " CHAR: %#x SAR: %#x DAR: %#x CNTR: %#x" in txx9dmac_dump_regs()
302 channel32_readl(dc, SAR), in txx9dmac_dump_regs()
316 channel_writeq(dc, SAR, 0); in txx9dmac_reset_chan()
320 channel_writel(dc, SAR, 0); in txx9dmac_reset_chan()
474 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR); in txx9dmac_dump_desc()
479 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR, in txx9dmac_dump_desc()
487 d->CHAR, d->SAR, d->DAR, d->CNTR); in txx9dmac_dump_desc()
492 d->CHAR, d->SAR, in txx9dmac_dump_desc()
[all...] |
| H A D | idma64.c | 94 channel_writeq(idma64c, SAR, 0); in idma64_chan_start()
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| /kernel/linux/linux-5.10/drivers/i2c/busses/ |
| H A D | i2c-rcar.c | 70 #define SAR (1 << 0) /* slave addr received */ macro
575 if (ssr_filtered & SAR) { in rcar_i2c_slave_irq()
580 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); in rcar_i2c_slave_irq()
584 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); in rcar_i2c_slave_irq()
588 rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff); in rcar_i2c_slave_irq()
595 rcar_i2c_write(priv, ICSIER, SAR); in rcar_i2c_slave_irq()
877 rcar_i2c_write(priv, ICSIER, SAR); in rcar_reg_slave()
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| /kernel/linux/linux-5.10/arch/sh/include/asm/ |
| H A D | dma-register.h | 14 #define SAR 0x00 /* Source Address Register */ macro
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| /kernel/linux/linux-6.6/arch/sh/include/asm/ |
| H A D | dma-register.h | 14 #define SAR 0x00 /* Source Address Register */ macro
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| /kernel/liteos_m/arch/xtensa/lx6/gcc/ |
| H A D | los_arch_macro.h | 83 wsr a3, SAR
122 rsr a3, SAR
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| H A D | los_window.S | 181 rsr a2, SAR
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| /kernel/linux/linux-6.6/drivers/i2c/busses/ |
| H A D | i2c-rcar.c | 70 #define SAR BIT(0) /* slave addr received */ macro
599 if (ssr_filtered & SAR) { in rcar_i2c_slave_irq()
604 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR); in rcar_i2c_slave_irq()
608 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR); in rcar_i2c_slave_irq()
612 rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff); in rcar_i2c_slave_irq()
619 rcar_i2c_write(priv, ICSIER, SAR); in rcar_i2c_slave_irq()
964 rcar_i2c_write(priv, ICSIER, SAR); in rcar_reg_slave()
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| /kernel/linux/linux-5.10/drivers/dma/sh/ |
| H A D | shdmac.c | 38 #define SAR 0x00 /* Source Address Register */ macro
217 sh_dmae_writel(sh_chan, hw->sar, SAR); in dmae_set_reg()
460 u32 sar_buf = sh_dmae_readl(sh_chan, SAR); in sh_dmae_desc_completed()
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| /kernel/linux/linux-6.6/drivers/dma/sh/ |
| H A D | shdmac.c | 37 #define SAR 0x00 /* Source Address Register */ macro
216 sh_dmae_writel(sh_chan, hw->sar, SAR); in dmae_set_reg()
459 u32 sar_buf = sh_dmae_readl(sh_chan, SAR); in sh_dmae_desc_completed()
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| /kernel/linux/linux-5.10/arch/xtensa/kernel/ |
| H A D | coprocessor.S | 118 /* Save remaining registers a1-a3 and SAR */
143 ssl a3 # SAR: 32 - coprocessor_number
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| /kernel/linux/linux-6.6/arch/xtensa/kernel/ |
| H A D | coprocessor.S | 152 /* Save remaining registers a1-a3 and SAR */
179 ssl a3 # SAR: 32 - coprocessor_number
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| /kernel/linux/linux-5.10/drivers/dma/dw/ |
| H A D | regs.h | 40 DW_REG(SAR); /* Source Address Register */
154 #define DWC_CTLL_SRC_INC (0<<9) /* SAR update/not */
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| H A D | core.c | 133 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", in dwc_dump_chan_regs()
134 channel_readl(dwc, SAR), in dwc_dump_chan_regs()
163 channel_writel(dwc, SAR, lli_read(desc, sar)); in dwc_do_single_block()
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| /kernel/linux/linux-5.10/arch/sh/drivers/dma/ |
| H A D | dma-sh.c | 217 * It's important that we don't accidentally write any value to SAR/DAR in sh_dmac_xfer_dma()
227 * SAR and DAR, regardless of value, in order for cascading to work. in sh_dmac_xfer_dma()
231 __raw_writel(chan->sar, (dma_base_addr(chan->chan) + SAR)); in sh_dmac_xfer_dma()
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| /kernel/linux/linux-6.6/arch/sh/drivers/dma/ |
| H A D | dma-sh.c | 217 * It's important that we don't accidentally write any value to SAR/DAR in sh_dmac_xfer_dma()
227 * SAR and DAR, regardless of value, in order for cascading to work. in sh_dmac_xfer_dma()
231 __raw_writel(chan->sar, (dma_base_addr(chan->chan) + SAR)); in sh_dmac_xfer_dma()
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| /kernel/linux/linux-6.6/drivers/dma/dw/ |
| H A D | regs.h | 40 DW_REG(SAR); /* Source Address Register */
154 #define DWC_CTLL_SRC_INC (0<<9) /* SAR update/not */
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| H A D | core.c | 130 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", in dwc_dump_chan_regs()
131 channel_readl(dwc, SAR), in dwc_dump_chan_regs()
160 channel_writel(dwc, SAR, lli_read(desc, sar)); in dwc_do_single_block()
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| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| H A D | sleep44xx.S | 148 ldreq r0, [r8, #L2X0_SAVE_OFFSET0] @ Retrieve L2 state from SAR
237 * stored in the SAR RAM while entering to OFF or DORMANT mode.
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| /kernel/linux/linux-6.6/arch/arm/mach-omap2/ |
| H A D | sleep44xx.S | 148 ldreq r0, [r8, #L2X0_SAVE_OFFSET0] @ Retrieve L2 state from SAR
237 * stored in the SAR RAM while entering to OFF or DORMANT mode.
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