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Searched refs:REG_SET_4 (Results 1 - 25 of 45) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dpp.c812 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0, in dpp3_program_shaper_luta_settings()
819 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0, in dpp3_program_shaper_luta_settings()
826 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0, in dpp3_program_shaper_luta_settings()
833 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0, in dpp3_program_shaper_luta_settings()
840 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0, in dpp3_program_shaper_luta_settings()
847 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0, in dpp3_program_shaper_luta_settings()
854 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0, in dpp3_program_shaper_luta_settings()
861 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0, in dpp3_program_shaper_luta_settings()
868 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0, in dpp3_program_shaper_luta_settings()
875 REG_SET_4(CM_SHAPER_RAMA_REGION_18_1 in dpp3_program_shaper_luta_settings()
[all...]
H A Ddcn30_mpc.c492 REG_SET_4(SHAPER_RAMA_REGION_0_1[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
499 REG_SET_4(SHAPER_RAMA_REGION_2_3[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
506 REG_SET_4(SHAPER_RAMA_REGION_4_5[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
513 REG_SET_4(SHAPER_RAMA_REGION_6_7[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
520 REG_SET_4(SHAPER_RAMA_REGION_8_9[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
527 REG_SET_4(SHAPER_RAMA_REGION_10_11[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
534 REG_SET_4(SHAPER_RAMA_REGION_12_13[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
541 REG_SET_4(SHAPER_RAMA_REGION_14_15[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
549 REG_SET_4(SHAPER_RAMA_REGION_16_17[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
556 REG_SET_4(SHAPER_RAMA_REGION_18_1 in mpc3_program_shaper_luta_settings()
[all...]
H A Ddcn30_dio_stream_encoder.c238 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
248 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
258 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
268 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
278 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
288 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
298 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
H A Ddcn30_vpg.c87 REG_SET_4(VPG_GENERIC_PACKET_DATA, 0, in vpg3_update_generic_info_packet()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dpp_cm.c605 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0, in dpp20_program_shaper_luta_settings()
612 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0, in dpp20_program_shaper_luta_settings()
619 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0, in dpp20_program_shaper_luta_settings()
626 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0, in dpp20_program_shaper_luta_settings()
633 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0, in dpp20_program_shaper_luta_settings()
640 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0, in dpp20_program_shaper_luta_settings()
647 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0, in dpp20_program_shaper_luta_settings()
654 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0, in dpp20_program_shaper_luta_settings()
661 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0, in dpp20_program_shaper_luta_settings()
668 REG_SET_4(CM_SHAPER_RAMA_REGION_18_1 in dpp20_program_shaper_luta_settings()
[all...]
H A Ddcn20_stream_encoder.c168 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
178 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
188 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
198 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
244 REG_SET_4(AFMT_GENERIC_HDR, 0, in enc2_update_gsp7_128_info_packet()
H A Ddcn20_dsc.c563 REG_SET_4(DSCC_CONFIG0, 0, in dsc_write_to_registers()
575 REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0, in dsc_write_to_registers()
644 REG_SET_4(DSCC_PPS_CONFIG12, 0, in dsc_write_to_registers()
650 REG_SET_4(DSCC_PPS_CONFIG13, 0, in dsc_write_to_registers()
656 REG_SET_4(DSCC_PPS_CONFIG14, 0, in dsc_write_to_registers()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dpp_cm.c605 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0, in dpp20_program_shaper_luta_settings()
612 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0, in dpp20_program_shaper_luta_settings()
619 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0, in dpp20_program_shaper_luta_settings()
626 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0, in dpp20_program_shaper_luta_settings()
633 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0, in dpp20_program_shaper_luta_settings()
640 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0, in dpp20_program_shaper_luta_settings()
647 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0, in dpp20_program_shaper_luta_settings()
654 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0, in dpp20_program_shaper_luta_settings()
661 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0, in dpp20_program_shaper_luta_settings()
668 REG_SET_4(CM_SHAPER_RAMA_REGION_18_1 in dpp20_program_shaper_luta_settings()
[all...]
H A Ddcn20_stream_encoder.c170 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
180 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
190 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
200 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc2_stream_encoder_stop_hdmi_info_packets()
247 REG_SET_4(AFMT_GENERIC_HDR, 0, in enc2_update_gsp7_128_info_packet()
H A Ddcn20_dsc.c608 REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE, in dsc_write_to_registers()
621 REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0, in dsc_write_to_registers()
690 REG_SET_4(DSCC_PPS_CONFIG12, 0, in dsc_write_to_registers()
696 REG_SET_4(DSCC_PPS_CONFIG13, 0, in dsc_write_to_registers()
702 REG_SET_4(DSCC_PPS_CONFIG14, 0, in dsc_write_to_registers()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_mpc.c368 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_0_1[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
375 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_2_3[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
382 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_4_5[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
389 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_6_7[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
396 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_8_9[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
403 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_10_11[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
410 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_12_13[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
417 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_14_15[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
425 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_16_17[mpcc_id], 0, in mpc32_program_shaper_luta_settings()
432 REG_SET_4(MPCC_MCM_SHAPER_RAMA_REGION_18_1 in mpc32_program_shaper_luta_settings()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dpp.c889 REG_SET_4(CM_SHAPER_RAMA_REGION_0_1, 0, in dpp3_program_shaper_luta_settings()
896 REG_SET_4(CM_SHAPER_RAMA_REGION_2_3, 0, in dpp3_program_shaper_luta_settings()
903 REG_SET_4(CM_SHAPER_RAMA_REGION_4_5, 0, in dpp3_program_shaper_luta_settings()
910 REG_SET_4(CM_SHAPER_RAMA_REGION_6_7, 0, in dpp3_program_shaper_luta_settings()
917 REG_SET_4(CM_SHAPER_RAMA_REGION_8_9, 0, in dpp3_program_shaper_luta_settings()
924 REG_SET_4(CM_SHAPER_RAMA_REGION_10_11, 0, in dpp3_program_shaper_luta_settings()
931 REG_SET_4(CM_SHAPER_RAMA_REGION_12_13, 0, in dpp3_program_shaper_luta_settings()
938 REG_SET_4(CM_SHAPER_RAMA_REGION_14_15, 0, in dpp3_program_shaper_luta_settings()
945 REG_SET_4(CM_SHAPER_RAMA_REGION_16_17, 0, in dpp3_program_shaper_luta_settings()
952 REG_SET_4(CM_SHAPER_RAMA_REGION_18_1 in dpp3_program_shaper_luta_settings()
[all...]
H A Ddcn30_mpc.c505 REG_SET_4(SHAPER_RAMA_REGION_0_1[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
512 REG_SET_4(SHAPER_RAMA_REGION_2_3[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
519 REG_SET_4(SHAPER_RAMA_REGION_4_5[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
526 REG_SET_4(SHAPER_RAMA_REGION_6_7[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
533 REG_SET_4(SHAPER_RAMA_REGION_8_9[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
540 REG_SET_4(SHAPER_RAMA_REGION_10_11[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
547 REG_SET_4(SHAPER_RAMA_REGION_12_13[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
554 REG_SET_4(SHAPER_RAMA_REGION_14_15[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
562 REG_SET_4(SHAPER_RAMA_REGION_16_17[rmu_idx], 0, in mpc3_program_shaper_luta_settings()
569 REG_SET_4(SHAPER_RAMA_REGION_18_1 in mpc3_program_shaper_luta_settings()
[all...]
H A Ddcn30_dio_stream_encoder.c224 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
234 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
244 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
254 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
264 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
274 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
284 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0, in enc3_stream_encoder_stop_hdmi_info_packets()
H A Ddcn30_vpg.c88 REG_SET_4(VPG_GENERIC_PACKET_DATA, 0, in vpg3_update_generic_info_packet()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_hpo_dp_stream_encoder.c378 REG_SET_4(DP_SYM32_ENC_VID_MSA0, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
384 REG_SET_4(DP_SYM32_ENC_VID_MSA1, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
390 REG_SET_4(DP_SYM32_ENC_VID_MSA2, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
396 REG_SET_4(DP_SYM32_ENC_VID_MSA3, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
402 REG_SET_4(DP_SYM32_ENC_VID_MSA4, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
408 REG_SET_4(DP_SYM32_ENC_VID_MSA5, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
414 REG_SET_4(DP_SYM32_ENC_VID_MSA6, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
420 REG_SET_4(DP_SYM32_ENC_VID_MSA7, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
426 REG_SET_4(DP_SYM32_ENC_VID_MSA8, 0, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_transform.c249 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0, in program_multi_taps_filter()
1515 REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0, in regamma_config_regions_and_segments()
1522 REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0, in regamma_config_regions_and_segments()
1529 REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0, in regamma_config_regions_and_segments()
1536 REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0, in regamma_config_regions_and_segments()
1543 REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0, in regamma_config_regions_and_segments()
1550 REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0, in regamma_config_regions_and_segments()
1557 REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0, in regamma_config_regions_and_segments()
1564 REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0, in regamma_config_regions_and_segments()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_transform.c249 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0, in program_multi_taps_filter()
1501 REG_SET_4(REGAMMA_CNTLA_REGION_0_1, 0, in regamma_config_regions_and_segments()
1508 REG_SET_4(REGAMMA_CNTLA_REGION_2_3, 0, in regamma_config_regions_and_segments()
1515 REG_SET_4(REGAMMA_CNTLA_REGION_4_5, 0, in regamma_config_regions_and_segments()
1522 REG_SET_4(REGAMMA_CNTLA_REGION_6_7, 0, in regamma_config_regions_and_segments()
1529 REG_SET_4(REGAMMA_CNTLA_REGION_8_9, 0, in regamma_config_regions_and_segments()
1536 REG_SET_4(REGAMMA_CNTLA_REGION_10_11, 0, in regamma_config_regions_and_segments()
1543 REG_SET_4(REGAMMA_CNTLA_REGION_12_13, 0, in regamma_config_regions_and_segments()
1550 REG_SET_4(REGAMMA_CNTLA_REGION_14_15, 0, in regamma_config_regions_and_segments()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_hubp.c74 REG_SET_4(DCN_EXPANSION_MODE, 0, in hubp201_program_requestor()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dpp_dscl.c282 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0, in dpp1_dscl_set_scaler_filter()
570 REG_SET_4(SCL_TAP_CONTROL, 0, in dpp1_dscl_set_scaler_auto_scale()
730 REG_SET_4(SCL_TAP_CONTROL, 0, in dpp1_dscl_set_scaler_manual_scale()
H A Ddcn10_stream_encoder.c97 REG_SET_4(AFMT_GENERIC_HDR, 0, in enc1_update_generic_info_packet()
456 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, in enc1_stream_encoder_dp_set_stream_attribute()
797 REG_SET_4(AFMT_GENERIC_HDR, 0, in enc1_stream_encoder_send_immediate_sdp_message()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.h76 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ macro
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.h76 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ macro
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_stream_encoder.c96 REG_SET_4(AFMT_GENERIC_HDR, 0, in enc1_update_generic_info_packet()
447 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, in enc1_stream_encoder_dp_set_stream_attribute()
825 REG_SET_4(AFMT_GENERIC_HDR, 0, in enc1_stream_encoder_send_immediate_sdp_message()
H A Ddcn10_dpp_dscl.c264 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0, in dpp1_dscl_set_scaler_filter()
688 REG_SET_4(SCL_TAP_CONTROL, 0, in dpp1_dscl_set_scaler_manual_scale()

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