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Searched refs:REG_MMU_PT_BASE_ADDR (Results 1 - 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/drivers/iommu/
H A Dmtk_iommu_v1.c37 #define REG_MMU_PT_BASE_ADDR 0x000 macro
232 writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_domain_finalise()
509 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_hw_init()
687 writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_resume()
H A Dmtk_iommu.c32 #define REG_MMU_PT_BASE_ADDR 0x000 macro
398 data->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_attach_device()
625 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_hw_init()
820 base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_resume()
/kernel/linux/linux-6.6/drivers/iommu/
H A Dmtk_iommu_v1.c34 #define REG_MMU_PT_BASE_ADDR 0x000 macro
266 writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_v1_domain_finalise()
571 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_v1_hw_init()
738 writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_v1_resume()
H A Dmtk_iommu.c37 #define REG_MMU_PT_BASE_ADDR 0x000 macro
758 writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_attach_device()
1097 writel_relaxed(0, bankx->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_hw_init()
1479 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_runtime_resume()

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