RADEON_VCLK_ECP_CNTL (reference) in projects: kernel - OpenGrok search results

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Searched refs:RADEON_VCLK_ECP_CNTL (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A D	radeon_clocks.c	526 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating() 529 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating() 579 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating() 582 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating() 732 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating() 736 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating() 768 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating() 772 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating() 819 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating() 823 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tm in radeon_legacy_set_clock_gating() [all...]
H A D	radeon_legacy_crtc.c	`945 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, in radeon_set_pll() 1017 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, in radeon_set_pll()`
H A D	radeon_legacy_encoders.c	`660 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_primary_dac_detect() 668 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_primary_dac_detect() 711 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl); in radeon_legacy_primary_dac_detect()`
H A D	radeon_reg.h	`1784 #define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */ macro`
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A D	radeon_clocks.c	526 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating() 529 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating() 579 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating() 582 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating() 732 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating() 736 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating() 768 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating() 772 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_set_clock_gating() 819 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_set_clock_gating() 823 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tm in radeon_legacy_set_clock_gating() [all...]
H A D	radeon_legacy_crtc.c	`945 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, in radeon_set_pll() 1017 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL, in radeon_set_pll()`
H A D	radeon_legacy_encoders.c	`653 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL); in radeon_legacy_primary_dac_detect() 661 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_primary_dac_detect() 704 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl); in radeon_legacy_primary_dac_detect()`
H A D	radeon_reg.h	`1784 #define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */ macro`

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